Semiconductor structure and manufacturing method thereof
A semiconductor structure is provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a via, an air gap, an etching stop layer, a second dielectric layer, and a second metal layer. The first metal layer is embedded in the first dielectric layer. The first metal layer includes a first conductive line and a second conductive line. The via is disposed on the first conductive line. The air gap is located on the second conductive line. The sustaining layer covers the air gap. The etching stop layer is disposed on the sustaining layer. The second dielectric layer is disposed on the etching stop layer. The second metal layer is disposed on the second dielectric layer and connected to the via.
1 . A manufacturing method of a semiconductor structure, comprising:
forming a first dielectric layer;
forming a first metal layer embodied in the first dielectric layer, wherein the first metal layer includes a first conductive line and a second conductive line;
forming a first concave and a second concave on the first conductive line and the second conductive line respectively;
forming a sacrificial material in the first concave, the second concave and on the first dielectric layer;
thinning down the sacrificial material to expose the first dielectric layer;
forming a sustaining layer on the sacrificial material and the first dielectric layer;
forming a third concave to expose the first conductive line;
removing the sacrificial material to form an air gap disposed between the sustaining layer and the second conductive line;
forming an etching stop layer on the sustaining layer and in the third concave;
forming a second dielectric layer on the etching stop layer; and
forming a via and a second metal layer, wherein the via is embedded in the second dielectric layer and connects the first conductive line, and the second metal layer is formed on the second dielectric layer to connect the via.
2 . The manufacturing method of the semiconductor structure according to claim 1 , wherein a width of the third concave is larger than a width of the second concave.
3 . The manufacturing method of the semiconductor structure according to claim 1 , wherein in the thinning down the sacrificial material, the sacrificial material is thinned down by chemical mechanical polish (CMP) process or etching process.
4 . The manufacturing method of the semiconductor structure according to claim 1 , wherein in the removing the sacrificial material, the sacrificial material is removed by a thermal process.
5 . The manufacturing method of the semiconductor structure according to claim 1 , wherein in the removing the sacrificial material, the sacrificial material is removed by UV, flash lamp or laser.
6 . The manufacturing method of the semiconductor structure according to claim 1 , wherein in the step of forming the first concave and the second concave, lateral walls of the first concave and the second concave expose the first dielectric layer.
7 . The manufacturing method of the semiconductor structure according to claim 1 , wherein in the step of forming the first concave and the second concave, a first barrier layer and a first liner layer are etched.
8 . The manufacturing method of the semiconductor structure according to claim 1 , wherein in the step of forming the third concave, the third concave expose a first liner layer and a first barrier layer.
9 . A manufacturing method of a semiconductor structure, comprising: forming a first dielectric layer; forming a first metal layer embodied in the first dielectric layer, wherein the first metal layer includes a first conductive line and two second conductive lines; forming a first concave on one of the two second conductive lines; forming a second concave on the other one of the two second conductive lines; forming a sacrificial material in the second concave in the first concave, the second concave and on the first dielectric layer; thinning down the sacrificial material to expose the first dielectric layer; forming a sustaining layer on the sacrificial material and the first dielectric layer; forming a third concave to expose the first conductive line; removing the sacrificial material to form an air gap disposed between the sustaining layer and one of the second conductive lines; forming an etching stop layer on the sustaining layer and in the third concave; forming a second dielectric layer on the etching stop layer; and forming a via and a second metal layer, wherein the via is embedded in the second dielectric layer and connects the first conductive line, and the second metal layer is formed on the second dielectric layer to connect the via.
10 . The manufacturing method of the semiconductor structure according to claim 9 , wherein a width of the third concave is larger than a width of the second concave.
11 . The manufacturing method of the semiconductor structure according to claim 9 , wherein in the thinning down the sacrificial material, the sacrificial material is thinned down by chemical mechanical polish (CMP) process or etching process.
12 . The manufacturing method of the semiconductor structure according to claim 9 , wherein in the removing the sacrificial material, the sacrificial material is removed by a thermal process.
13 . The manufacturing method of the semiconductor structure according to claim 9 , wherein in the step of forming the first concave and the second concave, lateral walls of the first concave and the second concave expose the first dielectric layer.
14 . The manufacturing method of the semiconductor structure according to claim 9 , wherein in the step of forming the first concave and the second concave, a first barrier layer and a first liner layer are etched.
15 . The manufacturing method of the semiconductor structure according to claim 9 , wherein in the step of forming the third concave, the third concave expose a first liner layer and a first barrier layer.
16 . A manufacturing method of a semiconductor structure, comprising:
forming a first dielectric layer;
forming a first metal layer embodied in the first dielectric layer, wherein the first metal layer includes a first conductive line and a second conductive line;
forming a first concave and a second concave on the first conductive line and the second conductive line respectively, wherein lateral walls of the first concave and the second concave expose a first liner layer;
forming a sacrificial material in the first concave, the second concave and on the first dielectric layer;
thinning down the sacrificial material to expose the first dielectric layer;
forming a sustaining layer on the sacrificial material and the first dielectric layer;
forming a third concave to expose the first conductive line;
removing the sacrificial material to form an air gap disposed between the sustaining layer and the second conductive line;
forming an etching stop layer on the sustaining layer and in the third concave;
forming a second dielectric layer on the etching stop layer; and
forming a via and a second metal layer, wherein the via is embedded in the second dielectric layer and connects the first conductive line, and the second metal layer is formed on the second dielectric layer to connect the via.
17 . The manufacturing method of the semiconductor structure according to claim 16 , wherein a width of the third concave is larger than a width of the second concave.
18 . The manufacturing method of the semiconductor structure according to claim 16 , wherein in the thinning down the sacrificial material, the sacrificial material is thinned down by chemical mechanical polish (CMP) process or etching process.
19 . The manufacturing method of the semiconductor structure according to claim 16 , wherein in the removing the sacrificial material, the sacrificial material is removed by a thermal process.
20 . The manufacturing method of the semiconductor structure according to claim 16 , wherein in the step of forming the third concave, the third concave expose the first liner layer and a first barrier layer.