Self-aligned via in double diffusion break to connect to backside interconnects
A microelectronic structure including a plurality of nanosheet transistors. Each of the plurality of nanosheet transistors includes an active gate located around a plurality of active channel layers and each of the plurality of nanosheet transistors includes a source/drain region have a first length. The first length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. A power via located between a first dummy device and a second dummy device and the power via has second length. The second length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. The second length is larger than the first length.
1 . A microelectronic structure comprising:
a plurality of nanosheet transistors, wherein each of the plurality of nanosheet transistors includes an active gate located around a plurality of active channel layers, wherein each of the plurality of nanosheet transistors includes a source/drain region having a first length, wherein the first length is measured perpendicular to a gate direction of the plurality of nanosheet transistors; and
a power via located between a first dummy device and a second dummy device, wherein the power via has a second length, wherein the second length is measured perpendicular to the gate direction of the plurality of nanosheet transistors, wherein the second length is larger than the first length, wherein each of the first dummy device and the second dummy device includes a gate, a plurality of channel layers, and an inner spacer, respectively.
2 . The microelectronic structure of claim 1 , wherein the power via includes a top section, a middle section, and a bottom section.
3 . The microelectronic structure of claim 2 , wherein the top section has a third length, wherein the third length is measured perpendicular to the gate direction of the plurality of nanosheet transistors, wherein the third length is larger than the second length.
4 . The microelectronic structure of claim 3 , wherein the power via has a shape of a bolt.
5 . The microelectronic structure of claim 4 , wherein a length of the middle section and the bottom section is the second length.
6 . The microelectronic structure of claim 5 , further comprising:
a spacer located adjacent to sidewalls of the bottom section of the power via, wherein the spacer extends along a height of the bottom section; and
a metal line connected to a bottom surface of the bottom section of the power via.
7 . The microelectronic structure of claim 6 , wherein the first dummy device and the second dummy devices are each comprised of a gate, a plurality of dummy channel layers, and an inner spacer, wherein each of the plurality of active channel layers has a first channel length, and each of the plurality of dummy channel layers has a second channel length, wherein the first and second channel length are measured perpendicular to the gate direction of the plurality of nanosheet transistors, wherein the second channel length is smaller than the first channel length.
8 . The microelectronic structure of claim 1 , wherein the power via has a first width as measured parallel to the gate direction of the plurality of nanosheet transistors, wherein the each of the plurality of transistors has a second width as measured parallel to the gate direction of the plurality of nanosheet transistors, wherein the first width is larger than the second width.
9 . A microelectronic structure comprising:
a plurality of nanosheet transistors, wherein each of the plurality of nanosheet transistors includes an active gate located around a plurality of active channel layers, wherein each of the plurality of nanosheet transistors includes a source/drain region having a first length, wherein the first length is measured perpendicular to a gate direction of the plurality of nanosheet transistors; and
a power via located between a first dummy device and a second dummy device, wherein the power via has a second length, wherein the second length is measured perpendicular to the gate direction of the plurality of nanosheet transistors, wherein the second length is larger than the first length, wherein the first dummy device is located flush against a first side of the power via and the second dummy device is located flush against a second side of the power via, wherein each of the first dummy device and the second dummy device includes a gate, a plurality of channel layers, and an inner spacer, respectively.
10 . The microelectronic structure of claim 9 , wherein the power via includes a top section, a middle section, and a bottom section.
11 . The microelectronic structure of claim 10 , wherein the top section has a third length, wherein the third length is measured perpendicular to the gate direction of the plurality of nanosheet transistors, wherein the third length is larger than the second length.
12 . The microelectronic structure of claim 11 , wherein the power via has a shape of a bolt.
13 . The microelectronic structure of claim 12 , wherein a length of the middle section and the bottom section is the second length.
14 . The microelectronic structure of claim 13 , further comprising:
a spacer located adjacent to sidewalls of the bottom section of the power via, wherein the spacer extends along a height of the bottom section; and
a metal line connected to a bottom surface of the bottom section of the power via.
15 . The microelectronic structure of claim 14 , wherein the first dummy device and the second dummy devices are each comprised of a gate, a plurality of dummy channel layers, and an inner spacer, wherein each of the plurality of active channel layers has a first channel length, and each of the plurality of dummy channel layers has a second channel length, wherein the first and second channel length are measured perpendicular to the gate direction of the plurality of nanosheet transistors wherein the second channel length is smaller than the first channel length.
16 . The microelectronic structure of claim 9 , wherein the power via has a first width as measured parallel to the gate direction of the plurality of nanosheet transistors, wherein the each of the plurality of transistors has a second width as measured parallel to the gate direction of the plurality of nanosheet transistors, wherein the first width is larger than the second width.
17 . The microelectronic structure of claim 9 , wherein the power via is a shared power via that extends across at least two nanosheet transistors, wherein the shared power via is located additionally between a third dummy device and a fourth dummy device.