Wet recess for Ru subtractive process
A semiconductor device includes a dielectric layer, a plurality of vias formed in the dielectric layer, an adhesion layer deposited on a top surface of the dielectric layer, and a plurality of metal lines. A first metal line of the plurality of metal lines includes a first recess formed at a bottom surface of the first metal line such that a first section of the first metal line directly contacts the first via and a second section of the first metal line defined by the first recess does not directly contact the first via or the dielectric layer in which the first via is formed.
1 . A semiconductor device, comprising:
a dielectric layer;
a plurality of vias in the dielectric layer, the plurality of vias comprising a first via;
an adhesion layer; and
a plurality of metal lines,
wherein a first metal line of the plurality of metal lines comprises a first recess at a bottom surface of the first metal line such that a first section of the first metal line directly contacts the first via and a second section of the first metal line defined by the first recess does not directly contact the first via or the dielectric layer having the first via therein,
wherein a second metal line of the plurality of metal lines comprises at least one second recess positioned between a bottom surface of the second metal line and the dielectric layer,
wherein the at least one second recess is defined by the bottom surface of the second metal line, a bottom surface of the adhesion layer, and a top surface of the dielectric layer, and
wherein the first metal line is free of overlap with the adhesion layer in a direction that is perpendicular to the top surface of the dielectric layer.
2 . The semiconductor device of claim 1 , wherein a first portion of the adhesion layer is positioned between the dielectric layer and the bottom surface of the second metal line such that the second metal line does not directly contact the dielectric layer.
3 . The semiconductor device of claim 2 , further comprising an oxide pattern positioned between the first portion of the adhesion layer and the dielectric layer.
4 . The semiconductor device of claim 3 , wherein the at least one second recess is defined by a side surface of the oxide pattern.
5 . A semiconductor device, comprising:
a dielectric layer;
a plurality of vias in the dielectric layer, the plurality of vias comprising a first via;
a plurality of metal lines; and
at least one oxide pattern positioned between a bottom surface of a first metal line of the plurality of metal lines and a top surface of the dielectric layer,
wherein the first metal line comprises at least one first recess positioned between the bottom surface of the first metal line and the dielectric layer,
wherein a second metal line of the plurality of metal lines comprises a second recess at a bottom surface of the second metal line such that a first section of the second metal line directly contacts the first via and a second section of the second metal line defined by the second recess does not directly contact the first via or the dielectric layer having the first via therein,
wherein the at least one first recess is defined by the bottom surface of the first metal line, a side surface of the at least one oxide pattern, and the top surface of the dielectric layer, and
wherein the second metal line is free of overlap with the at least one oxide pattern in a direction that is perpendicular to the top surface of the dielectric layer.
6 . The semiconductor device of claim 5 , wherein the plurality of metal lines comprise a ruthenium-based material.
7 . A method of fabricating a semiconductor device, comprising:
providing a base structure comprising a dielectric layer and a plurality of vias formed in the dielectric layer;
depositing an adhesion layer on a top surface of the dielectric layer;
patterning a plurality of metal lines on the base structure; and
forming at least one first recess at a bottom surface of a first metal line of the plurality of metal lines such that a first section of the first metal line directly contacts a first via of the plurality of vias and a second section of the first metal line defined by the at least one first recess does not directly contact the first via or the dielectric layer in which the first via is formed and/or between a bottom surface of a second metal line of the plurality of metal lines and the dielectric layer,
wherein the at least one first recess between the bottom surface of the second metal line and the dielectric layer is defined by the bottom surface of the second metal line, a bottom surface of the adhesion layer, and a top surface of the dielectric layer, and
wherein the first metal line is free of overlap with the adhesion layer in a direction that is perpendicular to the top surface of the dielectric layer.
8 . The method of claim 7 , wherein forming the at least one first recess comprises removing a portion of the adhesion layer positioned at the bottom surface of the first metal line, such that the at least one first recess is defined by a volume of the portion of the adhesion layer that is removed.
9 . The method of claim 8 , wherein the portion of the adhesion layer is removed by a titanium nitride wet recess process.
10 . The method of claim 7 , further comprising patterning an oxide material layer on the base structure prior to depositing the adhesion layer.
11 . The method of claim 10 , wherein the plurality of metal lines are patterned over the oxide material layer such that the oxide material layer is positioned between the bottom surface of the second metal line of the plurality of metal lines that does not interface with the plurality of vias-and the top surface of the dielectric layer in which the plurality of vias are formed.
12 . The method of claim 11 , wherein forming the at least one first recess comprises removing a portion of the adhesion layer at the bottom surface of the second metal line that does not interface with the plurality of vias, such that the at least one first recess is defined by the bottom surface of the second metal line that does not interface with the plurality of vias, a side surface of the oxide material layer, and the top surface of the dielectric layer.
13 . The method of claim 12 , wherein the at least one first recess is further defined by the bottom surface of the adhesion layer at the bottom surface of the second metal line that does not interface with the plurality of vias.
14 . The method of claim 7 , wherein the plurality of metal lines comprise a ruthenium-based material.
15 . The method of claim 7 , further comprising depositing a dielectric material between the patterned plurality of metal lines such that the dielectric material fills the at least one first recess.
16 . The method of claim 7 , further comprising, prior to depositing the adhesion layer, depositing a self-assembled monolayer (SAM) material on top surfaces of the plurality of vias such that, when the adhesion layer is deposited, the adhesion layer does not contact the plurality of vias.
17 . The method of claim 16 , wherein the adhesion layer is deposited over the SAM material, and
wherein the method further comprises removing the SAM material and portions of the adhesion layer deposited over the SAM material by a plasma treatment process.