IP Library Granted Patent US 12701988
Granted Patent B2
US 12701988 · App. 18/532,246 · Granted Aug 4, 2026

Metal interconnection structure of semiconductor device and method for forming the same

Inventors: Jianfeng Gao (Beijing, CN); Weibing Liu (Beijing, CN); Junjie Li (Beijing, CN); Na Zhou (Beijing, CN); Tao Yang (Beijing, CN); Junfeng Li (Beijing, CN); Jun Luo (Beijing, CN)
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
H10W20/435H10W20/033H10W20/056H10W20/077H10W20/081H10W20/42
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Quick Facts
Patent No.
US 12701988
App. No.
18/532,246
Granted
Aug 4, 2026
Kind
B2
Abstract

A metal interconnection structure of a semiconductor device and a method for forming the same. The method includes: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive structure in the first dielectric layer; etching back part of the first conductive structure; forming an etch stop layer on the first conductive structure; forming a second dielectric layer on the etch stop layer and performing chemical mechanical polishing; and forming a second conductive structure in the second dielectric layer, where the second conductive structure is electrically connected to the first conductive structure.

Claims (33)

1 . A method for forming a metal interconnection structure of a semiconductor device, comprising:

providing a substrate;

forming a first dielectric layer on the substrate;

forming a first conductive structure in the first dielectric layer;

etching back part of the first conductive structure;

forming an etch stop layer on the first conductive structure;

forming a second dielectric layer on the etch stop layer and performing chemical mechanical polishing; and

forming a second conductive structure in the second dielectric layer,

wherein the second conductive structure is electrically connected to the first conductive structure,

wherein the forming the first conductive structure in the first dielectric layer comprises: etching the first dielectric layer to form a trench; forming a first diffusion barrier layer in the trench, and then filling with a metal to obtain a metal layer,

wherein the etching back part of the first conductive structure comprises a two-step etching process, comprising: etching away part of the metal layer; and then etching away an exposed part of a sidewall of the first diffusion barrier layer.

2 . The method according to claim 1 , wherein the first dielectric layer and the second dielectric layer are made of a low-k material.

3 . The method according to claim 1 , wherein a material of the etch stop layer is one of SiN x or NSiC.

4 . The method according to claim 1 , wherein the forming a second conductive structure in the second dielectric layer comprises:

forming a through hole in the second dielectric layer by using a single damascene etching process;

forming a second diffusion barrier layer on a surface of the through hole; and

filling the through hole with a metal material.

5 . The method according to claim 1 , the forming a second conductive structure in the second dielectric layer comprises:

forming a trench and a through hole corresponding to the trench in the second dielectric layer by using a double damascene etching process;

forming a second diffusion barrier layer on a surface of the trench and a surface of the through hole; and

filling the trench and the through hole with a metal material.

6 . The method according to claim 4 , wherein the metal material is any one of W, Co, Cu, Ru, or Al.

7 . The method according to claim 5 , wherein the metal material is any one of W, Co, Cu, Ru, or Al.

8 . A metal interconnection structure of a semiconductor device, comprising:

a substrate;

a first dielectric layer on the substrate;

a first conductive structure in the first dielectric layer, wherein a surface of the first conductive structure is lower than a surface of the first dielectric layer;

an etch stop layer on the first conductive structure and the first dielectric layer;

a second dielectric layer on the etch stop layer; and

a second conductive structure in the second dielectric layer,

wherein the second conductive structure is electrically connected to the first conductive structure,

wherein the first conductive structure comprises a metal layer formed in the first dielectric layer and a first diffusion barrier layer between the metal layer and the first dielectric layer, and a surface of the first diffusion barrier layer is flush with a surface of the metal layer.

9 . The metal interconnection structure of the semiconductor device according to claim 8 , wherein the second conductive structure is a metal through hole or a combination of a metal through hole and a metal interconnection line.