Integrated isolation capacitor with enhanced bottom plate
An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 μm to 6.0 μm, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 μm to 1.0 μm.
1 . An electronic device, comprising:
a multilevel metallization structure over a semiconductor layer, the multilevel metallization structure having a first region, a second region, a pre-metal level over the semiconductor layer, and metallization structure levels over the pre-metal level, the pre-metal level and the metallization structure levels extending in respective planes of orthogonal first and second directions and arranged in a stack along a third direction that is orthogonal to the first and second directions, and the metallization structure levels including a first metallization structure level and a second metallization structure level;
a capacitor in the first region of the multilevel metallization structure, the capacitor having a first terminal and a second terminal, the first terminal forming a first capacitor plate in the first metallization structure level, the second terminal forming a second capacitor plate in the second metallization structure level, and the first terminal overlapping the second terminal by an overlap distance in the first and second directions, the overlap distance being 1.0 μm to 6.0 μm; and
a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield having interconnected metal lines and vias in the respective metallization structure levels that at least partially encircle the first region of the multilevel metallization structure, the conductive shield electrically connected to the semiconductor layer, the conductive shield including a first metal line that encircles the first terminal in the first metallization structure level, the first metal line spaced apart from the first terminal by a gap distance in the first and second directions, the gap distance being at least 0.5 μm and less than 1.0 μm.
2 . The electronic device of claim 1 , wherein the overlap distance is 2.0 μm to 5.0 μm.
3 . The electronic device of claim 2 , wherein the gap distance is 0.55 μm to 0.75 μm.
4 . The electronic device of claim 1 , wherein the gap distance is 0.55 μm to 0.75 μm.
5 . The electronic device of claim 1 , further comprising a bilayer structure in one of the metallization structure levels, the bilayer structure having a silicon oxynitride layer and a silicon nitride layer on the silicon oxynitride layer, the second terminal on a portion of the silicon nitride layer.
6 . The electronic device of claim 5 , further comprising a trench in the bilayer structure, the trench spaced laterally outward from the second terminal in the first and second directions, the trench extending through the silicon oxynitride layer along the third direction, the trench extending partially into the silicon oxynitride layer along the third direction, and the trench filled with dielectric material of the second metallization structure level.
7 . The electronic device of claim 1 , further comprising a transistor over or in the semiconductor layer.
8 . A packaged electronic device, comprising:
a semiconductor die, including:
a semiconductor layer;
a multilevel metallization structure over the semiconductor layer, the multilevel metallization structure having a first region, a second region, a pre-metal level on the semiconductor layer, and metallization structure levels over the pre-metal level, the pre-metal level and the metallization structure levels extending in respective planes of orthogonal first and second directions and arranged in a stack along a third direction that is orthogonal to the first and second directions, and the metallization structure levels including a first metallization structure level and a second metallization structure level;
a capacitor in the first region of the multilevel metallization structure, the capacitor having a first terminal and a second terminal, the first terminal forming a first capacitor plate in the first metallization structure level, the second terminal forming a second capacitor plate in the second metallization structure level; and, the first terminal overlapping the second terminal by an overlap distance in the first and second directions, the overlap distance being 1.0 μm to 6.0 μm, the second terminal including an exposed side; and
a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield having interconnected metal lines and vias in the respective metallization structure levels that at least partially encircle the first region of the multilevel metallization structure, the conductive shield coupled to the semiconductor layer, the conductive shield including a first metal line that encircles the first terminal in the first metallization structure level, the first metal line spaced apart from the first terminal by a gap distance in the first and second directions, the gap distance being at least 0.5 μm and less than 1.0 μm;
an electrical connection including an end bonded to the exposed side of the second terminal;
a package structure that encloses the semiconductor die and the electrical connection; and
conductive leads exposed along one or more sides of the package structure.
9 . The packaged electronic device of claim 8 , further comprising a second semiconductor die, including a conductive feature, the electrical connection including a second end bonded to the conductive feature of the second semiconductor die, and the package structure enclosing the second semiconductor die.
10 . The packaged electronic device of claim 8 , wherein the overlap distance is 2.0 μm to 5.0 μm.
11 . The packaged electronic device of claim 10 , wherein the gap distance is 0.55 μm to 0.75 μm.
12 . The packaged electronic device of claim 8 , wherein the gap distance is 0.55 μm to 0.75 μm.
13 . The packaged electronic device of claim 8 , further comprising a bilayer structure on one of the metallization structure levels, the bilayer structure having a silicon oxynitride layer and a silicon nitride layer on the silicon oxynitride layer, the second terminal on a portion of the silicon nitride layer.
14 . The packaged electronic device of claim 13 , further comprising a trench in the bilayer structure, the trench spaced laterally outward from the second terminal in the first and second directions, the trench extending through the silicon oxynitride layer along the third direction, the trench extending partially into the silicon oxynitride layer along the third direction, and the trench filled with dielectric material of the second metallization structure level.
15 . A method of forming an integrated circuit, comprising:
forming a multilevel metallization structure over a semiconductor layer, the multilevel metallization structure having: a first region; a second region; a capacitor in the first region; a pre-metal level on the semiconductor layer; metallization structure levels over the pre-metal level; and a conductive shield between the first region and the second region; the pre-metal level and the metallization structure levels extending in respective planes of orthogonal first and second directions and arranged in a stack along a third direction that is orthogonal to the first and second directions, and the metallization structure levels including a first metallization structure level and a second metallization structure level; the capacitor having a first terminal and a second terminal, the first terminal forming a first capacitor plate in the first metallization structure level, the second terminal forming a second capacitor plate in the second metallization structure level; the first terminal overlapping the second terminal by an overlap distance in the first and second directions, and the overlap distance being 1.0 μm to 6.0 μm; and the conductive shield having interconnected metal lines and vias in the respective metallization structure levels that at least partially encircle the first region of the multilevel metallization structure, the conductive shield coupled to the semiconductor layer, the conductive shield including a first metal line that encircles the first terminal in the first metallization structure level, the first metal line spaced apart from the first terminal by a gap distance in the first and second directions, and the gap distance being at least 0.5 μm and less than 1.0 μm;
separating a semiconductor die including the semiconductor layer and the multilevel metallization structure from a wafer;
forming an electrical connection to the second terminal of the capacitor; and
enclosing the semiconductor die and the electrical connection in a package structure with conductive leads exposed along one or more sides of the package structure.
16 . The method of claim 15 , wherein the overlap distance is 2.0 μm to 5.0 μm.
17 . The method of claim 15 , wherein the gap distance is 0.55 μm to 0.75 μm.
18 . The method of claim 15 , wherein forming the multilevel metallization structure comprises:
forming a bilayer structure in one of the metallization structure levels, the bilayer structure having a silicon oxynitride layer and a silicon nitride layer on the silicon oxynitride layer, the second terminal on a portion of the silicon nitride layer; and
forming a trench in the bilayer structure, the trench spaced laterally outward from the second terminal in the first and second directions, the trench extending through the silicon oxynitride layer along the third direction, the trench extending partially into the silicon oxynitride layer along the third direction, and the trench filled with dielectric material of the second metallization structure level.
19 . An integrated circuit, comprising:
an upper capacitor plate in an upper metal level over a semiconductor substrate, and a lower capacitor plate in a lower metal level over semiconductor substrate, the upper capacitor plate overlapping the lower capacitor plate such that the lower capacitor plate completely extends laterally beyond the upper capacitor plate by an overlap distance in a range from 1.0 μm to 6.0 μm; and
a ground ring in the lower metal level surrounding the lower capacitor plate, the ground ring and the lower capacitor plate being laterally spaced apart by a gap distance in a range from 0.5 μm to less than 1.0 μm.
20 . The integrated circuit of claim 19 , wherein the overlap distance is 2.0 μm to 5.0 μm.
21 . The integrated circuit of claim 19 , wherein the gap distance is 0.55 μm to 0.75 μm.
22 . The integrated circuit of claim 21 , wherein the overlap distance is 2.0 μm to 5.0.
23 . The integrated circuit of claim 19 , wherein the gap distance is about 0.55 μm and the overlap distance is about 3.0 μm.
24 . The integrated circuit of claim 19 , wherein the gap distance is 0.55 μm±0.25 μm and the overlap distance is about 3.0 μm±0.15 μm.