Apparatuses including metal-insulator-metal capacitor and methods for forming same

1 . A semiconductor structure, comprising:

an opening in a surface of a first insulating layer; and

a capacitor including:

a lower metal layer on the surface of the first insulating layer, and sidewalls and a bottom surface of the opening, wherein the sidewalls are tapered inwardly from the surface of the first insulating layer to the bottom surface of the opening by a taper angle of between 10 degrees and 45 degrees;

a dielectric layer on the lower metal layer;

an upper metal layer on the dielectric layer; and

an etch stop film on the upper metal layer and the lower metal layer, wherein the etch stop film contacts the upper metal layer and the lower metal layer.

2 . The semiconductor structure of claim 1 , wherein the first insulating layer is formed using silane (SiH 4 ) or tetraethoxysilane (Si(OC 2 H 5 ) 4 , TEOS).

3 . The semiconductor structure of claim 1 , wherein the lower metal layer comprises titanium nitride (TiN) or tantalum nitride (TaN).

4 . The semiconductor structure of claim 1 , wherein the dielectric layer comprises high-k dielectric material.

5 . The semiconductor structure of claim 4 , wherein the high-k dielectric material comprises hafnium (Hf)-containing high-k material, zirconium (Zr)-containing high-k material, aluminum (Al)-containing high-k material, or any combination thereof.

6 . The semiconductor structure of claim 1 , wherein the upper metal layer comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).

7 . The semiconductor structure of claim 1 , wherein the etch stop film further contacts a top surface of a potion of the lower metal layer, and wherein the portion of the lower metal layer extends beyond the dielectric layer and the upper metal layer.

8 . The semiconductor structure of claim 1 , wherein the etch stop film further contacts a top surface and a side surface of the upper metal layer and a side surface of the dielectric layer.

9 . A semiconductor structure, comprising:

an opening in a surface of a first insulating layer; and

a capacitor including:

a lower metal layer on the surface of the first insulating layer, and sidewalls and a bottom surface of the opening, wherein the sidewalls are tapered inwardly from the surface of the first insulating layer to the bottom surface of the opening by a taper angle of between 10 degrees and 45 degrees;

a dielectric layer on the lower metal layer;

an upper metal layer on the dielectric layer;

an etch stop film on the upper metal layer and the lower metal layer, wherein the etch stop film contacts the upper metal layer and the lower metal layer;

a second insulating layer on the first insulating layer and the capacitor;

a first interconnect electrically connected to the upper metal layer through the second insulating layer,

a second interconnect electrically connected to the lower metal layer through the second insulating layer, and

a third interconnect electrically connected to a second metal interconnect layer underlying the first insulating layer through the second insulating layer.

10 . A metal-insulator-metal (MIM) capacitor, comprising:

a lower metal layer continuously covering portions of a surface of a first insulating layer, sidewalls of a plurality of openings in the surface of the first insulating layer, and bottom surfaces of the plurality of openings;

a dielectric layer continuously covering the lower metal layer;

an upper metal layer continuously covering the dielectric layer; and

a first etch stop film on the upper metal layer and the lower metal layer, wherein the first etch stop film contacts the upper metal layer and a top surface of a portion of the lower metal layer, wherein the portion of the lower metal layer extends beyond the dielectric layer and the upper metal layer,

wherein the plurality of openings is formed in a two-dimensional array in a first direction and in a second direction that is perpendicular to the first direction.

11 . The MIM capacitor of claim 10 , wherein

the sidewalls at edges of each of the plurality of openings in the first direction are tapered inwardly from the surface of the first insulating layer to the bottom surface of the opening in the first direction by a taper angle of between 10 degrees and 45 degrees, and

the sidewalls at edges of each of the plurality of openings in the second direction are tapered inwardly from the surface of the first insulating layer to the bottom surface of the opening in the second direction by a tapered angle of between 10 degrees and 45 degrees.

12 . The MIM capacitor of claim 10 , further comprising:

a second insulating layer on the upper metal layer and the lower metal layer.

13 . A metal-insulator-metal (MIM) capacitor, comprising:

a lower metal layer continuously covering portions of a surface of a first insulating layer, sidewalls of a plurality of openings in the surface of the first insulating layer, and bottom surfaces of the plurality of openings;

a dielectric layer continuously covering the lower metal layer;

an upper metal layer continuously covering the dielectric layer;

a first etch stop film on the upper metal layer and the lower metal layer, wherein the first etch stop film contacts the upper metal layer and the lower metal layer;

a second insulating layer on the upper metal layer and the lower metal layer; and

a second etch stop film between the first insulating layer and an underlying insulating layer encapsulating a metal interconnect layer

wherein the plurality of openings is formed in a two-dimensional array in a first direction and in a second direction that is perpendicular to the first direction, and wherein the first etch stop film is between the second insulating layer and the upper metal layer and between the second insulating layer and the lower metal layer.

14 . The MIM capacitor of claim 13 , the first and second etch stop films comprise silicon carbide (SiC)-containing material.

15 . The MIM capacitor of claim 13 , further comprising:

a first interconnect extending through the second insulating layer to the first etch stop film;

a second interconnect extending through the second insulating layer to the lower metal layer; and

a third interconnect extending through the second insulating layer and the first insulating layer to the metal interconnect layer.