Semiconductor structures and methods of forming the same

1 . A method, comprising:

receiving a workpiece including a first conductive feature embedded in a dielectric layer;

forming a metal-insulator-metal (MIM) capacitor over the dielectric layer;

forming a first passivation structure over the MIM capacitor;

forming a first contact via opening extending through the first passivation structure and the MIM capacitor to expose the first conductive feature;

depositing a conductive material layer over the workpiece to fill the first contact via opening;

performing a first etching process to the conductive material layer to form a first metal feature, the first metal feature comprising a first portion filling the first contact via opening and a second portion over the first passivation structure, wherein a width of the second portion of the first metal feature gradually increases along a direction from a top surface of the first metal feature towards a bottom surface of the first metal feature; and

performing a second etching process to trim the second portion of the first metal feature, wherein, after the second etching process, in a cross-sectional view, a shape of the second portion of the first metal feature comprises a barrel shape.

2 . The method of claim 1 , wherein a bias power of the first etching process is different than a bias power of the second etching process.

3 . The method of claim 1 , wherein the first etching process and the second etching process implement a same etchant, and a flow rate of the etchant of the first etching process is different than a flow rate of the etchant of the second etching process.

4 . The method of claim 1 , wherein the second portion of the first metal feature comprises a lower sidewall surface and an upper sidewall surface, and the lower sidewall surface and a top surface of the first passivation structure forms an obtuse angle.

5 . The method of claim 1 , further comprising:

before the depositing of the conductive material layer, conformally depositing a barrier layer over the workpiece,

wherein the first portion of first metal feature further comprises a portion of the barrier layer in the first contact via opening, and the second portion of the first metal feature further comprises a portion of the barrier layer disposed on the first passivation structure.

6 . The method of claim 1 , further comprising:

after the performing of the second etching process, forming a second passivation structure over the first metal feature, wherein a composition of the second passivation structure is different than a composition of the first passivation structure.

7 . The method of claim 6 , further comprising:

before the performing of the first etching process, depositing an anti-reflective layer on the conducive material layer;

forming a patterned mask film on the anti-reflective layer; and

patterning the anti-reflective layer using the patterned mask film as an etch mask,

wherein the top surface of the first metal feature is spaced apart from the second passivation structure by the anti-reflective layer.

8 . The method of claim 7 , wherein the conducive material layer comprises aluminum (Al) or aluminum copper (Al-Cu), and the anti-reflective layer comprises silicon oxynitride (SiON).

9 . The method of claim 1 , wherein the workpiece further comprises a second conductive feature embedded in a dielectric layer, and the method further comprises:

forming a second contact via opening extending through the first passivation structure and the MIM capacitor to expose the second conductive feature; and

forming a second metal feature, wherein the second metal feature comprises a first portion filling the second contact via opening and a second portion over the first passivation structure, and a shape of cross-sectional view of the second portion of the second metal feature comprises a barrel shape.

10 . A method, comprising:

forming a metal-insulator-metal (MIM) capacitor over a substrate;

forming a dielectric layer over the MIM capacitor;

forming a conductive pad over the dielectric layer, wherein a bottom surface of the conductive pad is above a topmost surface of the MIM capacitor; and

forming a passivation structure on the dielectric layer and the conductive pad,

wherein a sidewall surface of the conductive pad comprises a lower portion and an upper portion, the lower portion and the bottom surface of the conductive pad forms a first angle, and the upper portion and the bottom surface of the conductive pad forms a second angle, wherein the first angle is different from the second angle, and the first angle is an obtuse angle.

11 . The method of claim 10 , wherein the forming of the conductive pad comprises:

depositing a barrier layer on a top surface of the dielectric layer;

depositing a conductive layer on the barrier layer;

etching the conductive layer and the barrier layer to form a conductive feature over the MIM capacitor; and

trimming a lower portion of the conductive feature to form the conductive pad.

12 . The method of claim 11 , wherein the etching of the conductive layer and the barrier layer comprises implementing an etchant under a first bias power, and the trimming of the lower portion of the conductive feature comprises implementing the etchant under a second bias power, the first bias power is different than the second bias power.

13 . The method of claim 11 , wherein the forming of the conductive pad comprises:

after the depositing of the conductive layer, forming an anti-reflective layer on the conductive layer;

forming a patterned mask film on the anti-reflective layer;

patterning the anti-reflective layer using the patterned mask film as an etch mask;

wherein the etching of the conductive layer and the barrier layer uses the patterned anti-reflective layer as an etch mask.

14 . The method of claim 13 , wherein a top surface of the conductive pad is spaced apart from the passivation structure by the patterned anti-reflective layer.

15 . The method of claim 10 , wherein the forming of the passivation structure comprises:

conformally depositing a first oxide layer over the conductive pad;

conformally depositing a first nitride layer over the first oxide layer;

forming an oxide liner over the first nitride layer;

depositing a second oxide layer over the oxide liner;

performing a planarization process to the second oxide layer; and

forming a second nitride layer over the second oxide layer.

16 . The method of claim 10 , wherein the second angle is an acute angle.

17 . A method, comprising:

depositing a conductive material layer over a dielectric layer;

forming a patterned mask over the conductive material layer, the patterned mask extending over a first portion of the conductive material layer, wherein a second portion of the conductive material layer is not covered by the patterned mask;

performing a first etching process to partially remove the second portion of the conductive material layer, wherein, upon completion of the performing of the first etching process, the conductive material layer has a top surface, a bottom surface, and a sidewall surface connecting the top surface and the bottom surface, wherein the sidewall surface is a linear sidewall surface; and

after the performing of the first etching process, performing a second etching process to trim a lower portion of the conductive material layer, wherein, upon completion of the performing of the second etching process, the sidewall surface of the conductive material layer becomes a non-linear sidewall surface.

18 . The method of claim 17 , wherein a bias power of the second etching process is less than a bias power of the first etching process.

19 . The method of claim 17 , wherein the first etching process and the second etching process implement a same etchant, and a flow rate of the etchant of the first etching process is greater than a flow rate of the etchant of the second etching process.

20 . The method of claim 17 , wherein, after the performing of the second etching process, the sidewall surface of the conductive material layer comprise a lower portion close to the dielectric layer and an upper portion away from the dielectric layer, and the lower portion and a topmost surface of the dielectric layer forms an obtuse angle.