Semiconductor package and method of manufacturing the semiconductor package

1 . A semiconductor package, comprising:

a first redistribution wiring layer having a plurality of first redistribution wires, and a plurality of first bonding pads electrically connected to the plurality of first redistribution wires and exposed from a lower surface of the first redistribution wiring layer;

a first semiconductor substrate on a first upper surface of the first redistribution wiring layer, the first semiconductor substrate having at least one first semiconductor chip and through vias that are electrically connected to the plurality of first redistribution wires, and the first semiconductor substrate having a first heat dissipation structure surrounding a first outer surface of the at least one first semiconductor chip;

a second redistribution wiring layer on the first semiconductor substrate, and the second redistribution wiring layer having a plurality of second redistribution wires that are electrically connected to the through vias; and

a second semiconductor substrate having at least one second semiconductor chip that is electrically connected to the plurality of second redistribution wires, and a second heat dissipation structure surrounding a second outer surface of the at least one second semiconductor chip,

wherein each of the first semiconductor substrate and the second semiconductor substrate further includes a cavity in which the at least one first semiconductor chip or the at least one second semiconductor chip is accommodated, and

each of the first heat dissipation structure and the second heat dissipation structure includes a liner film that covers an inner surface of the cavity and the first outer surface of the at least one first semiconductor chip and the second outer surface of the at least one second semiconductor chip, and a heat dissipation member in the liner film.

2 . The semiconductor package of claim 1 , wherein the second semiconductor substrate further includes at least one third semiconductor chip electrically connected to the plurality of second redistribution wires, and a third heat dissipation structure surrounding a third outer surface of the at least one third semiconductor chip.

3 . The semiconductor package of claim 1 , wherein the through vias include a first conductive material, and

each of the first heat dissipation structure and the second heat dissipation structure includes a second conductive material identical to the first conductive material.

4 . The semiconductor package of claim 3 , wherein the first conductive material and the second conductive material include at least one selected from copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn) or titanium (Ti).

5 . The semiconductor package of claim 1 , wherein the second redistribution wiring layer further includes second and third bonding pads that are electrically connected to and bonded to at least some of the plurality of second redistribution wires.

6 . The semiconductor package of claim 1 , further comprising:

a first lower redistribution wiring layer on the lower surface of the first redistribution wiring layer,

wherein the first lower redistribution wiring layer includes

first lower redistribution pads, at least some of the first lower redistribution pads bonded to at least some of the plurality of first bonding pads,

second lower redistribution pads exposed in an opposite direction to the first redistribution wiring layer, and

external connection bumps on the second lower redistribution pads.

7 . The semiconductor package of claim 6 , further comprising:

a sealing member on the first lower redistribution wiring layer, and the sealing member covering the first redistribution wiring layer and the second redistribution wiring layer and the first semiconductor substrate and the second semiconductor substrate;

conductive connectors penetrating the sealing member in a vertical direction, and the conductive connectors extending from the first lower redistribution pads that are not bonded to the plurality of first bonding pads; and

an upper redistribution wiring layer on a second upper surface of the sealing member, and the upper redistribution wiring layer having first upper redistribution pads provided on the conductive connectors.

8 . The semiconductor package of claim 6 , further comprising:

a conductive layer on the first lower redistribution wiring layer, the conductive layer having conductive wires electrically connected to the first lower redistribution pads that are not bonded to the plurality of first bonding pads, and insulating layers surrounding the conductive wires;

a sealing member on the first lower redistribution wiring layer, the sealing member covering a fourth outer surface of the first redistribution wiring layer and a fifth outer surface of the second redistribution wiring layer, the first semiconductor substrate and the second semiconductor substrate, and the conductive layer; and

an upper redistribution wiring layer on a second upper surface of the sealing member, the upper redistribution wiring layer having first upper redistribution pads provided on the conductive wires.

9 . The semiconductor package of claim 1 , wherein the first heat dissipation structure and the second heat dissipation structure are electrically insulated from the at least one first semiconductor chip and the at least one second semiconductor chip, respectively.

10 . A method of manufacturing a semiconductor package, the method comprising:

forming a first sub package having a first surface and a second surface opposed to each other;

forming a second sub package having a third surface and a fourth surface opposite to each other; and

bonding third bonding pads exposed from the fourth surface of the second sub package to second bonding pads exposed from the first surface of the first sub package,

wherein forming the first sub package includes,

forming a plurality of first openings and at least one first cavity, the plurality of first openings vertically penetrating a first semiconductor substrate that has a first upper surface and a first lower surface opposed to each other,

forming at least one first heat dissipation structure and through vias, the at least one first heat dissipation structure covering a first outer surface of at least one first semiconductor chip that is in the at least one first cavity, and the through vias into the plurality of first openings, respectively,

forming a first redistribution wiring layer having first bonding pads on the first lower surface of the first semiconductor substrate such that the first bonding pads electrically connected to the at least one first semiconductor chip and the through vias through a plurality of first redistribution wires are exposed to the second surface, and

forming a second redistribution wiring layer having the second bonding pads on the first upper surface of the first semiconductor substrate such that the second bonding pads electrically connected to the through vias through a plurality of second redistribution wires are exposed to the first surface,

wherein forming the second sub package includes

forming at least one second cavity penetrating a second semiconductor substrate in a vertical direction, the second semiconductor substrate having a second upper surface and a second lower surface opposite to each other,

forming at least one second heat dissipation structure covering a second outer surface of at least one second semiconductor chip that is in the at least one second cavity, and

forming a third redistribution wiring layer having the third bonding pads on the second lower surface of the second semiconductor substrate such that the third bonding pads electrically connected to the at least one second semiconductor chip through a plurality of third redistribution wires are exposed on the fourth surface, and

wherein the forming the at least one first heat dissipation structure and the through vias further includes

providing the at least one first semiconductor chip within the at least one first cavity,

forming the through vias by injecting a first conductive material into the plurality of first openings,

forming the at least one first heat dissipation structure by injecting the first conductive material between the at least one first cavity and the at least one first semiconductor chip, and

forming a liner film on the first outer surface of the at least one first semiconductor chip.

11 . The method of claim 10 , wherein the forming the through vias further includes forming the liner film on an inner surface of the at least one first cavity.

12 . The method of claim 10 , wherein the forming the at least one second heat dissipation structure further includes:

providing the at least one second semiconductor chip within the at least one second cavity; and

forming the at least one second heat dissipation structure by injecting a second conductive material between the at least one second cavity and the at least one second semiconductor chip.

13 . The method of claim 10 , wherein the forming the first sub package further includes:

forming at least one third cavity penetrating the second semiconductor substrate in the vertical direction;

forming at least one third heat dissipation structure covering a third outer surface of at least one third semiconductor chip that is in the at least one third cavity; and

forming the third redistribution wiring layer such that the at least one third semiconductor chip and the plurality of third redistribution wires are electrically connected to each other.

14 . The method of claim 10 , wherein the through vias and the at least one first heat dissipation structure and the at least one second heat dissipation structure include at least one selected from copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn) or titanium (Ti).

15 . The method of claim 10 , the method further comprising:

forming a lower redistribution wiring layer electrically connected to the first bonding pads on the second surface of the first sub package.

16 . The method of claim 15 , the method further comprising:

covering the first sub package and the second sub package on the lower redistribution wiring layer with a sealing member;

forming conductive connectors that penetrate the sealing member in the vertical direction from the lower redistribution wiring layer; and

forming a second substrate electrically connected to the lower redistribution wiring layer through the conductive connectors on a third upper surface of the sealing member.

17 . The method of claim 15 , the method further comprising:

forming a conductive layer on the lower redistribution wiring layer, the conductive layer having conductive wires that are electrically connected to the lower redistribution wiring layer, and insulating layers surrounding the conductive wires;

covering the conductive layer and the first sub package and the second sub package on the lower redistribution wiring layer through a sealing member; and

forming a second substrate electrically connected to the lower redistribution wiring layer through the conductive wires on a third upper surface of the sealing member.

18 . A method of manufacturing a semiconductor package, the method comprising:

forming a first sub package having a first surface and a second surface opposed to each other;

forming a second sub package having a third surface and a fourth surface opposite to each other; and

bonding third bonding pads exposed from the fourth surface of the second sub package to second bonding pads exposed from the first surface of the first sub package,

wherein forming the first sub package includes

forming a plurality of first openings and at least one first cavity, the plurality of first openings vertically penetrating a first semiconductor substrate that has a first upper surface and a first lower surface opposed to each other,

forming at least one first heat dissipation structure and through vias, the at least one first heat dissipation structure covering a first outer surface of at least one first semiconductor chip that is in the at least one first cavity, and the through vias into the plurality of first openings, respectively,

forming a first redistribution wiring layer having first bonding pads on the first lower surface of the first semiconductor substrate such that the first bonding pads electrically connected to the at least one first semiconductor chip and the through vias through a plurality of first redistribution wires are exposed to the second surface, and

forming a second redistribution wiring layer having the second bonding pads on the first upper surface of the first semiconductor substrate such that the second bonding pads electrically connected to the through vias through a plurality of second redistribution wires are exposed to the first surface,

wherein the forming the second sub package includes

forming at least one second cavity penetrating a second semiconductor substrate in a vertical direction, the second semiconductor substrate having a second upper surface and a second lower surface opposite to each other,

forming at least one second heat dissipation structure covering a second outer surface of at least one second semiconductor chip that is accommodated in the at least one second cavity, and

forming a third redistribution wiring layer having the third bonding pads on the second lower surface of the second semiconductor substrate such that the third bonding pads electrically connected to the at least one second semiconductor chip through a plurality of third redistribution wires are exposed on the fourth surface,

wherein the forming the at least one first heat dissipation structure and the through vias further includes

providing the at least one first semiconductor chip in the at least one first cavity,

forming the through vias by injecting a first conductive material into the plurality of first openings,

forming the at least one first heat dissipation structure by injecting the first conductive material between the at least one first cavity and the at least one first semiconductor chip, and

forming a liner film on the first outer surface of the at least one first semiconductor chip,

wherein the forming the second heat dissipation structure further includes

providing the at least one second semiconductor chip in the at least one second cavity, and

forming the at least one second heat dissipation structure by injecting a second conductive material between the at least one second cavity and the at least one second semiconductor chip, and

wherein the at least one first heat dissipation structure and the at least one second heat dissipation structure are electrically insulated from the at least one first semiconductor chip and the at least one second semiconductor chip.