IP Library Granted Patent US 12702002
Granted Patent B2
US 12702002 · App. 18/078,767 · Granted Aug 4, 2026

Double-sided heat dissipation power semiconductor module and method of manufacturing the same

Inventors: Deog Soo Kim (Daejeon, KR); Tae Ryong Kim (Daejeon, KR)
Assignee: LX SEMICON CO., LTD
H10W40/255H10W74/016H10W74/114H10W90/00H10W99/00H02P27/06H10W72/01235H10W72/072H10W72/223H10W72/255H10W90/724
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Quick Facts
Patent No.
US 12702002
App. No.
18/078,767
Granted
Aug 4, 2026
Kind
B2
Abstract

The present disclosure relates to a technology relating to a power semiconductor module of which heat is dissipated through both sides thereof and provides a technology for maintaining a distance between an upper substrate and a lower substrate by a metal bump formed on one side of a power semiconductor die.

Claims (19)

1 . A power semiconductor module comprising:

a die structure in which a metal bump is formed on one side of a power semiconductor die;

a first substrate to be electrically connected to a first electrode formed on the one side of the power semiconductor die through the metal bump; and

a second substrate to be electrically connected to a second electrode formed on another side of the power semiconductor die and to support the other side of the power semiconductor die,

wherein the metal bump is directly in contact with the one side of the power semiconductor die without a bonding layer,

wherein a lateral width of the metal bump is the same as that of the die structure,

wherein the metal bump is disposed on only the one side of the power semiconductor die,

wherein the die structure is bonded to the first substrate through a first bonding member disposed on one side of the metal bump and bonded to the second substrate through a second bonding member disposed on the other side of the power semiconductor die without a spacer disposed between the die structure and the first substrate or between the die structure and the second substrate, and

wherein the metal bump is formed through electroless plating on the one side of the power semiconductor die.

2 . The power semiconductor module of claim 1 , wherein the metal bump has a thickness predetermined in a range between 0.5 times and 2 times a thickness of the power semiconductor die.

3 . The power semiconductor module of claim 1 , wherein the metal bump is formed of a Cu-based metal.

4 . The power semiconductor module of claim 1 , wherein an epoxy molding compound (EMC) is disposed in a space between the die structure, the first substrate, and the second substrate.

5 . The power semiconductor module of claim 1 , wherein the first substrate comprises an insulating substance layer, a heat dissipation metal layer disposed on one side of the insulating substance layer, and a metal wiring layer disposed on the other side of the insulating substance layer.

6 . The power semiconductor module of claim 1 , wherein the metal bump is directly in contact with the one side of the power semiconductor die without the bonding layer including a solder layer.

7 . The power semiconductor module of claim 1 , wherein the die structure comprises a first power semiconductor die and a second power semiconductor die spaced apart from each other, and

wherein the metal bump comprises a first metal bump disposed only on a top surface of the first power semiconductor die, and a second metal bump disposed only on a bottom surface of the second power semiconductor die.

8 . The power semiconductor module of claim 1 , wherein a lateral width of the first bonding member is the same as that of the metal bump,

wherein a lateral width of the second bonding member is the same as that of the die structure, and

wherein a thickness of the metal bump is greater than that of the first bonding member.