Semiconductor package

1 . A semiconductor package comprising:

a first redistribution layer including a first wiring;

a die located on the first redistribution layer;

a shielding structure surrounding an upper surface and side surfaces of the die; and

a plurality of posts disposed outside the shielding structure on the first redistribution layer, and electrically connected to the first wiring,

wherein the shielding structure comprises:

a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die; and

a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die,

wherein upper surfaces of the shielding wall and the plurality of posts are coplanar with each other, and

wherein the shielding cover contacts the upper surface of the shielding wall.

2 . The semiconductor package of claim 1 , wherein the shielding wall is spaced apart from the die and the plurality of posts and between the die and the plurality of posts.

3 . The semiconductor package of claim 1 , wherein a vertical level of the upper surface of the shielding wall is higher than a vertical level of the upper surface of the die.

4 . The semiconductor package of claim 1 , wherein at least one of the shielding wall, the shielding cover, and the plurality of posts includes copper.

5 . The semiconductor package of claim 1 , further comprising a molding member which covers an upper surface of the first redistribution layer on the first redistribution layer, surrounds the die, the shielding wall, and the plurality of posts, and fills a space between the die, the shielding wall, and the plurality of posts.

6 . The semiconductor package of claim 5 , wherein the upper surfaces of the shielding wall and the plurality of posts are coplanar with an upper surface of the molding member.

7 . The semiconductor package of claim 5 , further comprising a second redistribution layer which is located on the shielding wall, the shielding cover, and the plurality of posts, and includes a second wiring that is electrically connected to the shielding wall and the plurality of posts.

8 . The semiconductor package of claim 7 , further comprising a top package that is located on the second redistribution layer and electrically connected to the second redistribution layer.

9 . The semiconductor package of claim 1 , wherein the shielding wall surrounds four sides of the die, and a shape of the shielding wall viewed from above is a quadrangular shape.

10 . The semiconductor package of claim 1 , wherein a space defined by the shielding wall completely overlaps a horizontal cross-section of the shielding cover in a vertical direction.

11 . A semiconductor package comprising:

a first redistribution layer including a first wiring;

a die located on the first redistribution layer;

a bump located between the first redistribution layer and the die and electrically connecting the die to the first wiring;

a shielding structure comprising a shielding wall that is spaced apart from side surfaces of the die and surrounds four sides of the die and a shielding cover which is spaced apart from an upper surface of the die and also surrounds the upper surface of the die, and has a flat lower surface, the shielding structure surrounding the die from the upper surface and the side surfaces of the die;

a plurality of posts located on the first redistribution layer and outside the shielding wall to be spaced apart from the shielding structure, the plurality of posts being electrically connected to the first wiring;

a molding member surrounding the die, the shielding wall, and the plurality of posts, and filling a space between the die, the shielding wall, and the plurality of posts;

a second redistribution layer which is located on the shielding wall, the shielding cover, and the plurality of posts, includes a second wiring, and is electrically connected to the shielding wall and the plurality of posts through the second wiring; and

an external connection terminal attached below the first redistribution layer,

wherein upper surfaces of the shielding wall and upper surfaces of the plurality of posts are coplanar with each other, and

wherein the shielding cover contacts the upper surface of the shielding wall.

12 . The semiconductor package of claim 11 , wherein a space defined by the shielding wall completely overlaps a horizontal cross-section of the shielding cover in a vertical direction.

13 . The semiconductor package of claim 11 , wherein the upper surfaces of the shielding wall and the plurality of posts are coplanar with an upper surface of the molding member.

14 . A semiconductor package comprising:

a first redistribution layer including a first wiring;

a die disposed on the first redistribution layer;

a shielding structure comprising a shielding wall that is spaced apart from side surfaces of the die and extends to continuously surround the side surfaces of the die, and a shielding cover that is spaced apart from an upper surface of the die and vertically overlaps the side surfaces of the die; and

a plurality of posts disposed on the first redistribution layer to be spaced apart from the shielding structure, the plurality of posts being electrically connected to the first wiring,

wherein the shielding wall is between the plurality of posts and the die,

wherein upper surfaces of the shielding wall and the plurality of posts are coplanar with each other, and

wherein the shielding cover contacts the upper surface of the shielding wall.

15 . The semiconductor package of claim 14 , further comprising:

a second redistribution layer disposed on the shielding wall, the shielding cover, and the plurality of posts, and including a second wiring,

wherein the second redistribution layer is electrically connected to the shielding wall and the plurality of posts through the second wiring.

16 . The semiconductor package of claim 14 , further comprising:

external connection terminals attached below the first redistribution layer.

17 . The semiconductor package of claim 14 , further comprising:

a molding member surrounding the die, the shielding wall, and the plurality of posts, and filling a space between the die, the shielding wall, and the plurality of posts.

18 . The semiconductor package of claim 14 , further comprising:

bumps between the first redistribution layer and the die,

wherein the bumps electrically connect the die to the first wiring.

19 . The semiconductor package of claim 14 , wherein the entire lower surface of the shielding cover is flat, the entire upper surface of the shielding cover is flat, or both the entire upper surface and the entire lower surface of the shielding cover are flat.