Semiconductor package with horizontally spaced chip and interposer substrate
A semiconductor package including: a first substrate; a first semiconductor chip and a second substrate horizontally spaced apart from each other on the first substrate; and a molding layer on the first substrate, the first semiconductor chip and the second substrate, wherein a thickness of the first semiconductor chip is greater than a thickness of the second substrate, wherein the molding layer exposes a top surface of the second substrate, and wherein the second substrate has fiducial marks exposed on the top surface of the second substrate.
1 . A semiconductor package, comprising:
a first substrate;
a first semiconductor chip and a second substrate horizontally spaced apart from each other on the first substrate; and
a molding layer on the first substrate, the first semiconductor chip and the second substrate,
wherein a thickness of the first semiconductor chip is greater than a thickness of the second substrate,
wherein the molding layer exposes a top surface of the second substrate, and
wherein the second substrate has fiducial marks exposed on the top surface of the second substrate.
2 . The semiconductor package of claim 1 , wherein a portion of a top surface of the molding layer is coplanar with the top surface of the second substrate.
3 . The semiconductor package of claim 1 , wherein a portion of a top surface of the molding layer is coplanar with a top surface of the first semiconductor chip.
4 . The semiconductor package of claim 1 , wherein the molding layer covers a top surface of the first semiconductor chip.
5 . The semiconductor package of claim 1 , further comprising a second semiconductor chip on the second substrate,
wherein the second semiconductor chip is on the second substrate and between the fiducial marks.
6 . The semiconductor package of claim 1 , wherein the first semiconductor chip includes a logic chip.