Semiconductor device and semiconductor chip
A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.
1 . A semiconductor device, comprising:
a plurality of chip regions on a substrate, each chip region of the plurality of chip regions including at least one circuit pattern for at least one integrated circuit device;
at least one scribe lane surrounding each chip region of the plurality of chip regions on the substrate;
a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions when viewed from a vertical direction; and
a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane when viewed from the vertical direction, wherein
the plurality of chip regions are separated from each other along the at least one scribe lane.
2 . The semiconductor device of claim 1 , wherein
a subset of chip regions of the plurality of chip regions are included in a shot group, the shot group having an area covered by a single exposure in a photolithography process; and
the plurality of first align key patterns and the plurality of first test element group patterns are included in each chip region of the subset of chip regions of the shot group.
3 . The semiconductor device of claim 2 , wherein
each of the plurality of first align key patterns included in each chip region of the subset of chip regions of the shot group include a plurality of align key patterns used in different exposure processes; and
the plurality of first test element group patterns included in each of the subset of chip regions of the shot group include a plurality of test patterns configured to provide a plurality of different tests of the semiconductor device.
4 . The semiconductor device of claim 1 , wherein
a first subset of chip regions of the plurality of chip regions are included in a shot group, the shot group having an area covered by a single exposure in a photolithography process;
the plurality of first align key patterns are included in the first subset of chip regions of the shot group; and
the plurality of first test element group patterns included in a second subset of chip regions of the plurality of chip regions of the shot group, the second subset of chip regions being different than the first subset of chip regions.
5 . The semiconductor device of claim 1 , further comprising:
a first region including the plurality of first align key patterns and the plurality of first test element group patterns, the first region being included at arbitrary positions within each chip region of the plurality of chip regions.
6 . The semiconductor device of claim 5 , wherein the first region is at the same position within each chip region of the plurality of chip regions.
7 . The semiconductor device of claim 5 , wherein the first region has a rectangular ring shape surrounding at least one edge of each chip region of the plurality of chip regions.
8 . The semiconductor device of claim 5 , wherein the first region is at a corner of an inner edge within each chip region of the plurality of chip regions.
9 . The semiconductor device of claim 5 , wherein
the at least one integrated circuit device is a plurality of integrated circuit devices; and
the plurality of integrated circuit devices are included in a main region in each chip region of the plurality of chip regions, the main region being different than the first region in each chip region of the plurality of chip regions.
10 . A semiconductor device, comprising:
a plurality of integrated circuit devices;
a shot group of a substrate, the shot group including a plurality of chip regions, the shot group having an area covered by a single shot of a photolithography process;
at least one scribe lane on the substrate, the at least one scribe lane surrounding the plurality of chip regions;
a first region included in each chip region of the plurality of chip regions, the first region including at least one of a plurality of first align key patterns and a plurality of first test element group patterns when viewed from a vertical direction; and
a main region included in each chip region of the plurality of chip regions, the main region including the plurality of integrated circuit devices,
the plurality of first align key patterns included in the plurality of chip regions of the shot group include a plurality of align key patterns used in different exposure processes, and the plurality of first test element group patterns included in the plurality of chip regions of the shot group include a plurality of patterns configured to provide a plurality of different tests of the plurality of integrated circuit devices, wherein the plurality of chip regions are separated from each other along the at least one scribe lane.
11 . The semiconductor device of claim 10 , wherein the at least one scribe lane includes at least one of a plurality of second align key patterns and a plurality of second test element group patterns.
12 . The semiconductor device of claim 10 , wherein the at least one scribe lane does not include a plurality of second align key patterns and a plurality of second test element group patterns.
13 . The semiconductor device of claim 10 , wherein each chip region of the plurality of chip regions include the plurality of first align key patterns and the plurality of first test element group patterns.
14 . The semiconductor device of claim 10 , wherein
the shot group includes a first subset of chip regions and a second subset of chip regions;
the first subset of chip regions includes the plurality of first align key patterns; and
the second subset of chip regions includes the plurality of first test element group patterns.
15 . The semiconductor device of claim 10 , wherein the first region is at arbitrary positions within each chip region of the plurality of chip regions.
16 . The semiconductor device of claim 10 , wherein the first region is at the same position within each chip region of the plurality of chip regions.
17 . A semiconductor chip, comprising:
a plurality of integrated circuit devices;
a chip region;
at least one scribe lane surrounding the chip region;
a first region included in the chip region, the first region including a plurality of first align key patterns and a plurality of first test element group patterns when viewed from a vertical direction; and
a main region included in the chip region, the main region including the plurality of integrated circuit devices, wherein the chip region is separated from other chip regions along the at least one scribe lane.
18 . The semiconductor chip of claim 17 , wherein the at least one scribe lane includes at least one of cut portions of a plurality of second align key patterns and cut portions of a plurality of second test element group patterns.
19 . The semiconductor chip of claim 17 , wherein the at least one scribe lane does not include a plurality of second align key patterns and a plurality of second test element group patterns.
20 . The semiconductor chip of claim 17 , wherein the first region is at an arbitrary position within the chip region.