IP Library › Granted Patent US 12702019
Granted Patent B2
US 12702019 · App. 18/336,313 · Granted Aug 4, 2026

Semiconductor package

Inventors: Kanggyune Lee (Suwon-si, KR); Sangwon Lee (Suwon-si, KR); Woojin Choi (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10W46/607H10W40/10H10W46/00H10W46/401H10W74/117H10W72/20H10W74/014H10W90/00H10W90/24H10W90/722H10W90/724
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Quick Facts
Patent No.
US 12702019
App. No.
18/336,313
Granted
Aug 4, 2026
Kind
B2
Abstract

A semiconductor package includes a package substrate, a first semiconductor chip on the package substrate, a sealing layer on the package substrate and at least partially covering the first semiconductor chip and including an upper surface, a first side surface, and a first inclined surface extending between the upper surface and the first side surface, and a first marking pattern in or on the first inclined surface of the sealing layer.

Claims (50)

1 . A semiconductor package comprising:

a package substrate;

a first semiconductor chip on the package substrate;

a sealing layer on the package substrate and at least partially covering the first semiconductor chip, the sealing layer comprising an upper surface extending in a first direction, a first side surface that extends in a second direction transverse to the first direction, and a first inclined surface having a first portion and a second portion, each of the first portion and the second portion extending between and in a third direction transverse to the upper surface and the first side surface; and

a first information marking pattern in or on the first portion of the first inclined surface of the sealing layer,

wherein no information marking pattern is in or on the second portion of the first inclined surface of the sealing layer.

2 . The semiconductor package of claim 1 , wherein the sealing layer covers an upper surface of the first semiconductor chip.

3 . The semiconductor package of claim 1 , wherein the upper surface of the sealing layer is coplanar with an upper surface of the first semiconductor chip.

4 . The semiconductor package of claim 3 , wherein the upper surface of the first semiconductor chip is exposed to an outside of the semiconductor package.

5 . The semiconductor package of claim 3 , further comprising a heat dissipation member attached to the upper surface of the first semiconductor chip.

6 . The semiconductor package of claim 1 , wherein the sealing layer further comprises a second side surface and a second inclined surface extending between the upper surface and the second side surface of the sealing layer, and

wherein the semiconductor package further comprises a second marking pattern in or on the second inclined surface of the sealing layer.

7 . The semiconductor package of claim 1 , further comprising a second semiconductor chip stacked on the first semiconductor chip,

wherein a distance in a first lateral direction between the first side surface of the sealing layer and the second semiconductor chip is greater than a distance in the first lateral direction between the first side surface of the sealing layer and the first semiconductor chip, and

wherein the first lateral direction is perpendicular to the first side surface of the sealing layer.

8 . The semiconductor package of claim 7 , wherein the sealing layer further comprises a second side surface and a second inclined surface extending between the upper surface and the second side surface of the sealing layer,

wherein the semiconductor package further comprises a second marking pattern in or on the second inclined surface of the sealing layer,

wherein a distance in a second lateral direction between the second side surface of the sealing layer and the second semiconductor chip is greater than a distance in the second lateral direction between the second side surface of the sealing layer and the first semiconductor chip, and

wherein the second lateral direction is perpendicular to the second side surface of the sealing layer.

9 . The semiconductor package of claim 8 , wherein the first side surface of the sealing layer and the second side surface of the sealing layer are connected to each other.

10 . The semiconductor package of claim 1 , wherein the first side surface extends parallel to a first plane, the first inclined surface extends parallel to a second plane, and an angle between the first plane and the second plane is about 10 degrees to about 80 degrees.

11 . The semiconductor package of claim 1 , wherein the sealing layer comprises a first sealing layer on the package substrate and a second sealing layer on the first sealing layer,

wherein the second sealing layer comprises the first inclined surface, and

at least one of a photosensitive material and a thermosensitive material.

12 . The semiconductor package of claim 1 , further comprising a photoreactive material layer on the first inclined surface of the sealing layer, the photoreactive material layer comprising at least one of a photosensitive material and a thermosensitive material, and

wherein the first information marking pattern is in the photoreactive material layer.

13 . The semiconductor package of claim 1 , wherein the first information marking pattern comprises a groove in the first inclined surface of the sealing layer.

14 . The semiconductor package of claim 1 , wherein the first information marking pattern comprises a material layer applied to the first inclined surface of the sealing layer, and wherein a surface roughness of the first inclined surface is greater than a surface roughness of the upper surface of the sealing layer and a surface roughness of the first side surface of the sealing layer.

15 . A semiconductor package comprising:

a package substrate;

a chip structure on an upper surface of the package substrate and comprising a plurality of semiconductor chips stacked in a first direction that is perpendicular to the upper surface of the package substrate;

a sealing layer on the package substrate and at least partially covering the chip structure, the sealing layer comprising an upper surface extending in a second direction, a first side surface that extends in the first direction transverse to the second direction, and a first inclined surface extending between and transverse to the upper surface and the first side surface; and

a first marking pattern in or on the first inclined surface of the sealing layer, the first marking pattern having a portion that is in or on the first inclined surface and overlies and is aligned with at least one of the plurality of semiconductor chips in the first direction,

wherein a distance in a first lateral direction between a first one of the plurality of semiconductor chips and the first side surface of the sealing layer is greater than a distance in the first lateral direction between a lower second one of the plurality of semiconductor chips and the first side surface of the sealing layer.

16 . The semiconductor package of claim 15 , wherein the sealing layer further comprises a second side surface and a second inclined surface extending between the upper surface and the second side surface of the sealing layer,

wherein the semiconductor package further comprises a second marking pattern in or on the second inclined surface of the sealing layer, and,

wherein a distance in a second lateral direction between the first one of the plurality of semiconductor chips and the second side surface of the sealing layer is greater than a distance in the second lateral direction between the second one of the plurality of semiconductor chips and the second side surface of the sealing layer.

17 . The semiconductor package of claim 15 , wherein an upper surface of an uppermost one of the plurality of semiconductor chips is coplanar with the upper surface of the sealing layer.

18 . The semiconductor package of claim 17 , further comprising a heat dissipation member attached to the upper surface of the uppermost one of the plurality of semiconductor chips.

19 . The semiconductor package of claim 15 , wherein the first marking pattern is configured to visually convey information about the semiconductor package.

20 . A semiconductor package comprising:

a package substrate;

a chip structure on an upper surface of the package substrate and comprising a plurality of semiconductor chips stacked in a first direction that is perpendicular to the upper surface of the package substrate;

a sealing layer on the package substrate and at least partially covering the chip structure, the sealing layer comprising an upper surface extending in a second direction, a first side surface that extends in the first direction transverse to the second direction, a second side surface, a first inclined surface having a first portion and a second portion, each of the first portion and the second portion extending between and in a third direction transverse to the upper surface and the first side surface, and a second inclined surface extending between the upper surface and the second side surface;

a first information marking pattern in or on the first portion of the first inclined surface of the sealing layer and overlying at least one of the plurality of semiconductor chips in the first direction; and

a second marking pattern in or on the second inclined surface of the sealing layer and overlying at least one of the plurality of semiconductor chips,

wherein the first inclined surface of the sealing layer and the second inclined surface of the sealing layer are connected to each other,

wherein a distance in a first lateral direction between a first one of the plurality of semiconductor chips and the first side surface of the sealing layer is greater than a distance in the first lateral direction between a lower second one of the plurality of semiconductor chips and the first side surface of the sealing layer,

wherein a distance in a second lateral direction between the first one of the plurality of semiconductor chips and the second side surface of the sealing layer is greater than a distance in the second lateral direction between the second one of the plurality of semiconductor chips and the second side surface of the sealing layer, and

wherein no information marking pattern is in or on the second portion of the first inclined surface of the sealing layer.