IP Library Granted Patent US 12702022
Granted Patent B2
US 12702022 · App. 18/162,679 · Granted Aug 4, 2026

Package structure and method of forming the same

Inventors: Chih-Wei Wu (Yilan County, TW); Wen-Chih Chiou (Miaoli County, TW); Ying-Ching Shih (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10W70/611H10W70/05H10W70/685H10W74/01H10W90/00H10W90/701H10W72/252H10W90/724H10W90/754
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Quick Facts
Patent No.
US 12702022
App. No.
18/162,679
Granted
Aug 4, 2026
Kind
B2
Abstract

Provided are a package structure having a joint structure and a method of forming the same. The package structure includes: a first under bump metallurgy (UBM) structure disposed on a first dielectric layer, wherein the first UBM structure at least comprises: a barrier layer embedded in the first dielectric layer; and an upper metal layer disposed over the barrier layer, wherein a sidewall of the barrier layer is laterally offset outward from a sidewall of the upper metal layer, and a portion of a top surface of the barrier layer is exposed by the first dielectric layer; and a solder layer disposed on the first UBM structure and contacting the upper metal layer.

Claims (41)

1 . A package structure having a joint structure, the joint structure comprising:

a first under bump metallurgy (UBM) structure, at least comprising:

a barrier layer, embedded in a first dielectric layer; and

an upper metal layer, covering a first portion of a top surface of the barrier layer to expose a second portion of the top surface of the barrier layer, wherein a width measured by opposite sidewalls of the barrier layer is greater than a width measured by opposite sidewalls of the upper metal layer, and the second portion of the top surface of the barrier layer is exposed by the first dielectric layer; and

a solder layer, disposed on the first UBM structure and contacting the upper metal layer.

2 . The package structure of claim 1 , wherein a non-zero distance is included between the sidewall of the barrier layer and the sidewall of the upper metal layer, and the non-zero distance is in a range from 0.5 μm to 20 μm.

3 . The package structure of claim 1 , further comprising: a lower metal layer, wherein the barrier layer is vertically sandwiched between the lower metal layer and the upper metal layer.

4 . The package structure of claim 3 , wherein a material of the barrier layer is different from a material of the lower metal layer and/or the upper metal layer.

5 . The package structure of claim 3 , wherein the barrier layer comprises:

a main body portion, embedded in the first dielectric layer and vertically sandwiched between the lower metal layer and the upper metal layer; and

a protruding portion, extending from a sidewall of the main body portion to cover a portion of a top surface of the first dielectric layer.

6 . The package structure of claim 5 , wherein the protruding portion has a bottom surface in direct contact with the portion of the top surface of the first dielectric layer.

7 . The package structure of claim 1 , wherein a top surface of the first dielectric layer is substantially level with or lower than the top surface of the barrier layer.

8 . The package structure of claim 1 , further comprising: an intermetallic compound (IMC) layer disposed between the solder layer and the upper metal layer.

9 . The package structure of claim 1 , further comprising:

a second UBM structure disposed on a second dielectric layer, wherein the solder layer is sandwiched between the first UBM structure and the second UBM structure.

10 . The package structure of claim 1 , further comprising: an opening disposed in the first dielectric layer and laterally surrounding the upper metal layer and the solder layer, wherein the opening exposes the second portion of the top surface of the barrier layer.

11 . A package structure having a joint structure, the joint structure comprising:

an UBM structure, comprising:

a first metal layer embedded in a dielectric layer;

a second metal layer disposed on the first metal layer; and

a barrier layer vertically disposed between the first metal layer and the second metal layer, wherein an interface between the barrier layer and the first metal layer is higher than a top surface of the dielectric layer, and the barrier layer is configured to have a metal material that is more difficult to form an intermetallic compound (IMC) than the second metal layer;

a solder layer, overlying a top surface and a sidewall of the second metal layer; and

an IMC layer, disposed between and being in contact with the solder layer and the second metal layer.

12 . The package structure of claim 11 , wherein a sidewall of the barrier layer protrudes from the sidewall of the second metal layer to a non-zero distance, and the non-zero distance is in a range from 0.5 μm to 20 μm.

13 . The package structure of claim 11 , wherein the first metal layer comprises:

a lower portion, embedded in the dielectric layer; and

an upper portion, disposed on the lower portion and extending to cover a portion of a top surface of the dielectric layer.

14 . The package structure of claim 11 , further comprising: a bond pad disposed over a package substrate, wherein the solder layer is sandwiched between the UBM structure and the bond pad.

15 . A package structure having a joint structure, the joint structure comprising:

an UBM structure, at least comprising:

a barrier layer, embedded in a dielectric layer; and

an upper metal layer, disposed over the barrier layer, wherein a sidewall of the barrier layer is laterally offset outward from a sidewall of the upper metal layer; and

a solder layer, disposed on the UBM structure and contacting the upper metal layer; and

an opening disposed in the dielectric layer and laterally surrounding the upper metal layer and the solder layer, wherein the opening exposes a portion of a top surface of the barrier layer.

16 . The package structure of claim 15 , wherein a non-zero distance is included between the sidewall of the barrier layer and the sidewall of the upper metal layer, and the non-zero distance is in a range from 0.5 μm to 20 μm.

17 . The package structure of claim 15 , further comprising: a lower metal layer, wherein the barrier layer is vertically sandwiched between the lower metal layer and the upper metal layer.

18 . The package structure of claim 17 , wherein a material of the barrier layer is different from a material of the lower metal layer and/or the upper metal layer.

19 . The package structure of claim 15 , wherein the opening extends from the top surface of the dielectric layer to the top surface of the barrier layer.

20 . The package structure of claim 15 , further comprising:

a bond pad disposed over a package substrate, wherein the solder layer is sandwiched between the UBM structure and the bond pad.