Circuit board
A circuit board including a first insulating layer; a first circuit pattern layer disposed on the first insulating layer and including a first pad; a second circuit pattern layer disposed on a lower surface of the first insulating layer; and a first electrode part disposed in the first insulating layer and vertically overlapping the first pad. A lower surface of the first electrode part is located higher than an upper surface of the second circuit pattern layer, and the first pad includes a first concave portion formed in a region that vertically overlaps the first electrode part.
1 . A circuit board, comprising:
a first insulating layer;
a first circuit pattern layer disposed on the first insulating layer and including a first pad;
a second circuit pattern layer disposed on a lower surface of the first insulating layer; and
a first electrode part disposed in the first insulating layer and vertically overlapping the first pad, wherein a lower surface of the first electrode part is located higher than an upper surface of the second circuit pattern layer, wherein the first pad includes a first concave portion formed in an upper surface of the first pad in a region that vertically overlaps the first electrode part, wherein an upper surface of the first electrode part is in direct contact with a lower surface of the first pad, and wherein the lower surface of the first electrode part is spaced apart in a vertical direction from the upper surface of the second circuit pattern layer.
2 . The circuit board of claim 1 , wherein a thickness of the first electrode part satisfies a range of 20% to 80% of a thickness of the first insulating layer, and wherein the thickness of the first insulating layer is a vertical distance between a lower surface of the first circuit pattern layer and the upper surface of the second circuit pattern layer.
3 . The circuit board of claim 1 , wherein the first pad includes a first-first portion that vertically overlaps the first electrode part, and a first-second portion that does not vertically overlap the first electrode part, and wherein the first concave portion is provided at the first-first portion of the first pad.
4 . The circuit board of claim 3 , wherein an upper surface of the first-second portion of the first pad includes a curved surface whose height decreases as it moves away from the first-first portion.
5 . The circuit board of claim 1 , wherein the first circuit pattern layer includes a second pad spaced apart from the first pad in a horizontal direction, wherein a second electrode part is provided to pass through the first insulating layer vertically overlapping the second pad, wherein an upper surface of the second electrode part is in direct contact with a lower surface of the second pad, and wherein a lower surface of the second electrode part is in direct contact with the second circuit pattern layer.
6 . The circuit board of claim 5 , wherein the second pad includes a second concave portion formed in a region that vertically overlaps the second electrode part.
7 . The circuit board of claim 6 , wherein a width of the first electrode part corresponds to a width of the second electrode part, and wherein a depth of the first concave portion is smaller than a depth of the second concave portion.
8 . The circuit board of claim 6 , wherein a width of the first electrode part is greater than a width of the second electrode part, and wherein a depth of the first concave portion corresponds to a depth of the second concave portion.
9 . The circuit board of claim 8 , wherein the width of the first electrode part satisfies a range of 120% to 180% of the width of the second electrode part.
10 . The circuit board of claim 5 , wherein a surface roughness of the lower surface of the first electrode part is greater than a surface roughness of the lower surface of the second electrode part.
11 . The circuit board of claim 5 , wherein the lower surface of the first electrode part includes at least one of a first curved surface convex toward the first circuit pattern layer and a second curved surface convex toward the second circuit pattern layer.
12 . The circuit board of claim 1 , further comprising:
a second electrode part passing through the first insulating layer, wherein an upper surface of the second electrode part is in direct contact with the first pad and a lower surface of the second electrode part is in direct contact with the upper surface of the second circuit pattern layer, wherein the first pad includes a first region vertically overlapping with the first electrode part and a second region that vertically overlaps the second electrode part, and wherein the first concave portion is formed on an upper surface of the first region of the first pad, and the first pad includes a second concave portion formed on an upper surface of the second region.
13 . The circuit board of claim 1 , further comprising:
a first protective layer disposed on an upper surface of the first insulating layer, wherein the first protective layer includes a first portion having a height lower than a height of the first pad and disposed surrounding a side surface of the first pad.
14 . The circuit board of claim 1 , wherein the first electrode part has an inclination where a width in a horizontal direction decreases along a vertical direction.
15 . The circuit board of claim 14 , wherein the second electrode part has an inclination inclined in a same direction as a direction of the inclination of the first electrode portion.
16 . A semiconductor package, comprising:
a first insulating layer;
a first circuit pattern layer including a first pad and a second pad disposed on the first insulating layer;
a second circuit pattern layer disposed on a lower surface of the first insulating layer;
a first electrode part disposed in the first insulating layer and vertically overlapping the first pad;
a second electrode part disposed in the first insulating layer and vertically overlapping the second pad;
a first connection part disposed on the first pad and the second pad;
a chip mounted on the first connection part; and
a molding layer for molding the chip, wherein the first electrode part has a thickness less than a thickness of the first insulating layer, wherein the second electrode part has a thickness corresponding to the thickness of the first insulating layer, wherein the first pad includes a first concave portion formed in an upper surface of the first pad in a region that vertically overlaps the first electrode part, wherein the second pad includes a second concave portion formed in a region that vertically overlaps the second electrode part, wherein an upper surface of the first electrode part is in direct contact with a lower surface of the first pad, and wherein the lower surface of the first electrode part is spaced apart in a vertical direction from the upper surface of the second circuit pattern layer.
17 . The semiconductor package of claim 16 , wherein the first connection part includes a first-first connection part disposed on the first pad and filling the first concave portion; and a first-second connection part disposed on the second pad and filling the second concave portion.
18 . The semiconductor package of claim 16 , wherein the chip includes a first chip and a second chip that are spaced apart from each other in a width direction or arranged in a vertical direction on the first insulating layer.