Semiconductor package

1 . A circuit board comprising:

an insulating layer;

a first pad disposed under a lower surface of the insulating layer;

a second pad disposed on an upper surface of the insulating layer; and

a through electrode part passing through the insulating layer and connecting the first pad and the second pad,

wherein the insulating layer has a thickness in a range of 40 μm to 70 μm,

wherein a width of the second pad in a first horizontal direction exceeds 15 times the thickness of the insulating layer,

wherein the through electrode part includes a plurality of first through electrodes spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction,

wherein each of the plurality of first through electrodes includes a first sub through electrode and a second sub through electrode spaced apart from each other in the first horizontal direction,

wherein the first sub through electrode and the second sub through electrode of each of the plurality of first through electrodes have a first width in the first horizontal direction greater than a second width in the second horizontal direction,

wherein the first width is greater than the thickness of the insulating layer and no greater than 25 times the thickness of the insulating layer,

wherein, in each of the plurality of first through electrodes, a first separation distance between the first sub through electrode and the second sub through electrode in the first horizontal direction is smaller than the second width,

wherein a second separation distance in the second horizontal direction between the first sub through electrodes of two adjacent first through electrodes among the plurality of first through electrodes is smaller than the second width, and

wherein the first separation distance is smaller than the second separation distance.

2 . The circuit board of claim 1 , wherein lower surfaces of the plurality of first through electrodes are in common connected with an upper surface of the first pad.

3 . The circuit board of claim 1 , wherein upper surfaces of the plurality of first through electrodes are in common connected with a lower surface of the second pad.

4 . The circuit board of claim 1 , wherein a width of a lower surface of each of the plurality of first through electrodes is smaller than a width of an upper surface of each of the plurality of first through electrodes.

5 . The circuit board of claim 4 , wherein each of the plurality of first through electrodes has an inclination in which a width gradually decreases from the upper surface to the lower surface.

6 . The circuit board of claim 1 , further comprising:

a via electrode part passing through the insulating layer and spaced apart from the through electrode part in the first and second horizontal directions.

7 . The circuit board of claim 6 , wherein widths of the via electrode part in the first and second horizontal directions are smaller than the first width and the second width.

8 . The circuit board of claim 6 , wherein the via electrode part is provided closer to an outer surface of the insulating layer than the through electrode part.

9 . A semiconductor package comprising:

an insulating layer;

a first pad disposed under a lower surface of the insulating layer;

a second pad disposed on an upper surface of the insulating layer;

a through electrode part passing through the insulating layer and connecting the first pad and the second pad;

an adhesive member disposed on the second pad; and

a semiconductor chip disposed on the adhesive member,

wherein the insulating layer has a thickness in a range of 40 μm to 70 μm,

wherein a width of the second pad in a first horizontal direction exceeds 15 times the thickness of the insulating layer,

wherein the through electrode part includes a plurality of first through electrodes spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction,

wherein each of the plurality of first through electrodes includes a first sub through electrode and a second sub through electrode spaced apart from each other in the first horizontal direction,

wherein the first sub through electrode and the second sub through electrode of each of the plurality of first through electrodes have a first width in the first horizontal direction greater than a second width in the second horizontal direction,

wherein the first width is greater than the thickness of the insulating layer and no greater than 25 times the thickness of the insulating layer,

wherein, in each of the plurality of first through electrodes, a first separation distance between the first sub through electrode and the second sub through electrode in the first horizontal direction is smaller than the second width,

wherein a second separation distance in the second horizontal direction between the first sub through electrodes of two adjacent first through electrodes among the plurality of first through electrodes is smaller than the second width, and

wherein the first separation distance is smaller than the second separation distance.

10 . The semiconductor package of claim 9 , wherein lower surfaces of the plurality of first through electrodes are in common connected with an upper surface of the first pad; and

wherein upper surfaces of the plurality of first through electrodes are commonly connected to lower surfaces of the second pad.

11 . The semiconductor package of claim 9 , wherein a width of a lower surface of each of the plurality of first through electrodes is smaller than a width of an upper surface of each of the plurality of first through electrodes; and

wherein each of the plurality of first through electrodes has an inclination in which a width gradually decreases from the upper surface to the lower surface.