IP Library Granted Patent US 12702030
Granted Patent B2
US 12702030 · App. 17/948,332 · Granted Aug 4, 2026

Power module and method for manufacturing same

Inventors: Hyeon Uk Kim (Hwaseong, KR); Hyun Koo Lee (Seoul, KR); Jun Hee Park (Hwaseong, KR)
Assignees: Hyundai Motor Company; Kia Corporation
H10W70/658H10W70/041H10W70/047H10W70/479H10W90/401H10W90/701H10W72/865H10W72/868H10W72/884H10W72/886H10W90/734H10W90/755H10W90/765
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Quick Facts
Patent No.
US 12702030
App. No.
17/948,332
Granted
Aug 4, 2026
Kind
B2
Abstract

Disclosed are a power module and a method for manufacturing the same. A power module according to an embodiment of the present disclosure includes: a first substrate; a second substrate disposed spaced apart from the first substrate and including at least one metal layer; at least one chip disposed between the first substrate and the second substrate and in electrical contact with the metal layer; and a third substrate configured to be disposed spaced apart from the first substrate and the second substrate, electrically connect the chip and at least one external input terminal, include one or more conductive patterns each of which is connected to one of the at least one lead frame, and be formed in a multi-layer structure such that the one or more conductive patterns are not short-circuited to each other.

Claims (32)

1 . A power module comprising:

a first substrate;

a second substrate spaced apart from the first substrate and comprising at least one metal layer;

at least one chip disposed between the first substrate and the second substrate and in electrical contact with the at least one metal layer; and

a third substrate spaced apart from the first substrate and the second substrate, and electrically connecting the at least one chip and at least one lead frame, the third substrate comprising one or more conductive patterns,

wherein each of the conductive patterns is connected to one lead frame of the at least one lead frame, and is formed in a multi-layer circuit structure such that the one or more conductive patterns are not short-circuited to each other,

wherein each of the conductive patterns is disposed on a different layer of the third substrate such that even though crossing and passing on the same plane, the different conductive patterns are spaced apart from each other in space so as to prevent short-circuiting between the conductive patterns,

wherein the at least one lead frame comprises a first lead frame in electrical contact with the at least one metal layer,

wherein the chip receives power through the first lead frame and the at least one metal layer,

wherein the at least one lead frame comprises a second lead frame spaced apart from the first substrate and the second substrate, and

wherein the third substrate is disposed on the second lead frame.

2 . The power module of claim 1 ,

wherein the second lead frame is electrically connected to at least one external input terminal of a plurality of external input terminals such that the chip receives an external input signal through the second lead frame and the third substrate.

3 . The power module of claim 2 ,

wherein the chip is electrically connected to the third substrate through wire or metal clip bonding.

4 . The power module of claim 3 ,

wherein the third substrate comprises a plurality of wire bonding holes, and the at least one chip is bonded to one wire bonding hole of the plurality of wire bonding holes, and

wherein the plurality of wire bonding holes are connected to the different external input terminals via the different second lead frames.

5 . The power module of claim 3 ,

wherein the third substrate comprises a plurality of metal clip bonding parts,

wherein the chip is bonded to one metal clip bonding part of the plurality of metal clip bonding parts, and

wherein each metal clip bonding part of the plurality of metal clip bonding parts is connected to different external input terminals via different second lead frames.

6 . The power module of claim 1 ,

wherein the conductive patterns are formed in a stereoscopic structure, such that even though crossing and passing on the same plane, the different conductive patterns are spaced apart from each other in space.

7 . The power module of claim 1 , further comprising:

a spacer configured to allow the first substrate and the second substrate to be spaced a predetermined distance apart from each other.

8 . The power module of claim 1 ,

wherein the chip is in electric contact with the spacer.

9 . The power module of claim 8 ,

wherein a contact agent is applied between the chip and the spacer.

10 . The power module of claim 1 ,

wherein a contact agent is applied between the chip and the metal layer.