High-density microbump arrays with enhanced adhesion and methods of forming the same
A semiconductor die may include metal interconnect structures located within interconnect-level dielectric material layers, bonding pads located on a topmost interconnect-level dielectric material layer, a dielectric passivation layer located on the topmost interconnect-level dielectric material layer, and metal bump structures extending through the dielectric passivation layer and located on the bonding pads. Each of the metal bump structures comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of a respective one of the bonding pads, a tapered surface segment in contact with a tapered sidewall of a respective opening through the dielectric passivation layer, and an annular surface segment that overlies the dielectric passivation layer and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of a respective underlying one of the bonding pads.
1 . A semiconductor structure comprising a semiconductor die, wherein the semiconductor die comprises:
a metal interconnect structure located within interconnect-level dielectric material layers;
a bonding pad located on a topmost interconnect-level dielectric material layer and electrically connected to the metal interconnect structure, wherein the bonding pad comprises a pad plate portion having a bottom surface in contact with a horizontal surface segment of a top surface of the topmost interconnect-level dielectric layer within a first horizontal plane and further comprises a via portion that vertically extends from the first horizontal plane downward through the topmost interconnect-level dielectric layer and contacts a sidewall of the topmost interconnect-level dielectric layer and contacts a top surface of the metal interconnect structure;
a dielectric passivation layer located on the top surface of the topmost interconnect-level dielectric material layer, wherein the dielectric passivation layer comprises a dielectric passivation material which is selected from silicon nitride or silicon carbide nitride, conformally covers, and contacts, all sidewall surfaces of the bonding pad, peripheral surface segments of a top surfaces of the bonding pad, and the top surface of the topmost interconnect-level dielectric layer in a vertical cross-sectional view, and has a uniform material composition throughout; and
a metal bump structure extending through the dielectric passivation layer and located on the bonding pad, wherein the metal bump structure comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of the bonding pad, a tapered surface segment in contact with a tapered sidewall of an opening through the dielectric passivation layer, and an annular surface segment that overlies the dielectric passivation layer and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of an underlying bonding pad, wherein the annular surface segment is located above, and is vertically spaced from, a second horizontal plane including topmost surface segments of the dielectric passivation layer and is in contact with a dielectric surface.
2 . The semiconductor structure of claim 1 , wherein the dielectric passivation layer comprises a horizontally-extending segment contacting the topmost interconnect-level dielectric material layer, vertically-extending segments contacting sidewalls of the bonding pad, and capping segments contacting an annular peripheral portion of a top surface of the bonding pad.
3 . The semiconductor structure of claim 1 , further comprising a capping dielectric material layer overlying the dielectric passivation layer, wherein the metal bump structure comprises an additional tapered surface segment in contact with a tapered sidewall of an opening through the capping dielectric material layer.
4 . The semiconductor structure of claim 3 , wherein the capping dielectric material layer comprises an additional dielectric passivation material.
5 . The semiconductor structure of claim 4 , wherein the additional dielectric passivation material is selected from silicon nitride or silicon carbide nitride.
6 . The semiconductor structure of claim 3 , wherein the capping dielectric material layer comprises a polymer material.
7 . The semiconductor structure of claim 3 , wherein the capping dielectric material layer comprises a horizontal top surface that extends over areas that are not covered by the metal bump structure and located within a third horizontal plane that contains the annular surface segment of the metal bump structure.
8 . The semiconductor structure of claim 3 , wherein:
the annular surface segment of the metal bump structure contacts an annular surface segment of the capping dielectric material layer; and
the metal bump structure comprises an additional annular surface segment in contact with an annular surface segment of a top surface of a capping segment of the dielectric passivation layer that overlies of the bonding pad.
9 . The semiconductor structure of claim 1 , wherein the metal bump structure is located entirely within an area of the underlying bonding pad in a plan view along a direction that is perpendicular to a top surface of the topmost interconnect-level dielectric material layer.
10 . The semiconductor structure of claim 1 , further comprising an interconnect-containing structure comprises an additional metal bump structure and selected from a second semiconductor die, an interposer, or a packaging substrate, wherein the metal bump structure of the semiconductor die is bonded to the additional metal bump structure of the interconnect-containing structure through solder material portions.
11 . The semiconductor structure of claim 10 , further comprising an underfill material portion contacting the solder material portions, the metal bump structure of the semiconductor die, and the additional metal bump structure of the interconnect-containing structure.
12 . The semiconductor structure of claim 3 , further comprising an underfill material portion contacting the metal bump structure of the semiconductor die, and a horizontal top surface of the capping dielectric material layer, and does not contact any surface of the dielectric passivation layer or the bonding pad, wherein an entirety of an interface between the underfill material portion and the horizontal top surface of the capping dielectric material layer is located within a third horizontal plane including the annular surface segment of the metal bump structure.
13 . A semiconductor structure comprising a first semiconductor die and an interconnect-containing structure, wherein the first semiconductor die comprises:
a first metal interconnect structure located within first interconnect-level dielectric material layers;
a first bonding pad located on a topmost first interconnect-level dielectric material layer and electrically connected to the first metal interconnect structure, wherein the first bonding pad comprises a pad plate portion having a bottom surface in contact with a horizontal surface segment of a top surface of the topmost interconnect-level dielectric layer within a first horizontal plane and further comprises a via portion that vertically extends from the first horizontal plane downward through the topmost interconnect-level dielectric layer and contacts a respective sidewall of the topmost interconnect-level dielectric layer and contacts a top surface of the metal interconnect structures;
a dielectric passivation layer located on the topmost first interconnect-level dielectric material layer and the first bonding pad, wherein the dielectric passivation layer comprises a dielectric passivation material which is selected from silicon nitride or silicon carbide nitride, conformally covers, and contacts, all sidewall surfaces of the first bonding pad, peripheral surface segments of a top surface of the first bonding pad, and the top surface of the topmost interconnect-level dielectric layer in a vertical cross-sectional view, and has a uniform material composition throughout;
a first metal bump structure extending through the dielectric passivation layer and located on the first bonding pad; and
a capping dielectric material layer contacting the dielectric passivation layer and the contoured bottom surface of the first metal bump structure, wherein the first metal bump structure comprises an additional tapered surface segment in contact with a tapered sidewall of an opening through the capping dielectric material layer, and wherein an underfill material portion contacts the capping dielectric material layer, wherein:
the first metal bump structure comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of the first bonding pad, and an annular surface segment that overlies the dielectric passivation layer and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8% of a width of an underlying first bonding pad;
the annular surface segment is located above, and is vertically spaced from, a second horizontal plane including topmost surface segments of the dielectric passivation layer and is in contact with a dielectric surface;
the interconnect-containing structure comprises a second metal bump structure and is selected from a second semiconductor die, an interposer, or a packaging substrate;
the first metal bump structure is bonded to the second metal bump structure through solder material portions; and
the metal bump structure comprises an additional annular surface segment located within the second horizontal plane and in contact with an annular surface segment of a top surface of a capping segment of the dielectric passivation layer that overlies the bonding pad.
14 . The semiconductor structure of claim 13 , wherein:
the capping dielectric material layer comprises an additional dielectric passivation material selected from silicon nitride or silicon carbide nitride.
15 . The semiconductor structure of claim 14 , wherein: the capping dielectric material layer comprises a horizontal top surface that extends over areas that are not covered by the first metal bump structure and located within a plane that contains the annular surface segment of the first metal bump structure.
16 . A semiconductor structure comprising a semiconductor die, wherein the semiconductor die comprises:
a metal interconnect structure located within interconnect-level dielectric material layers;
a bonding pad located on a topmost interconnect-level dielectric material layer and electrically connected to the metal interconnect structure, wherein the bonding pad comprises a pad plate portion having a bottom surface in contact with a horizontal surface segment of a top surface of the topmost interconnect-level dielectric layer within a first horizontal plane and further comprises a via portion that vertically extends from the first horizontal plane downward through the topmost interconnect-level dielectric layer and contacts a sidewall of the topmost interconnect-level dielectric layer and contacts a top surface of the metal interconnect structure;
a dielectric passivation layer located on the topmost interconnect-level dielectric material layer, wherein the dielectric passivation layer comprises a dielectric passivation material which is selected from silicon nitride or silicon carbide nitride, conformally covers, and contacts, all sidewall surfaces of the bonding pads, peripheral surface segments of top surfaces of the bonding pads, and the top surface of the topmost interconnect-level dielectric layer in a vertical cross-sectional view, and has a uniform material composition throughout;
a capping dielectric material layer overlying the dielectric passivation layer; and
metal bump structures extending through the dielectric passivation layer and the capping dielectric material layer and located on the bonding pad, wherein the metal bump structure comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of the bonding pad, a tapered surface segment in contact with a tapered sidewall of an opening through the dielectric passivation layer, and a first annular surface segment that contacts a second annular surface segment of the capping dielectric material layer.
17 . The semiconductor structure of claim 16 , wherein the dielectric passivation layer comprises a horizontally-extending segment contacting the topmost interconnect-level dielectric material layer, vertically-extending segments contacting sidewalls of the bonding pad, and capping segments contacting an annular peripheral portion of a top surface of the bonding pad.
18 . The semiconductor structure of claim 16 , wherein the metal bump structure comprises an additional tapered surface segment in contact with a tapered sidewall of a respective opening through the capping dielectric material layer.
19 . The semiconductor structure of claim 18 , wherein the capping dielectric material layer comprises an additional dielectric passivation material that is selected from silicon nitride or silicon carbide nitride.
20 . The semiconductor structure of claim 16 , wherein:
the metal bump structure comprises an additional annular surface segment which is located within a second horizontal plane including topmost surface segments of the dielectric passivation layer and is in contact with a respective annular surface segment of a top surface of a capping segment of the dielectric passivation layer that overlies the bonding pad; and
the annular surface segment of the metal bump structure is located within a third horizontal plane including a top surface of the capping dielectric material layer.