Substrate trench for improved hybrid bonding
Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.
1 . An apparatus, comprising:
a substrate comprising a pedestal surrounded by a recessed surface, wherein a bonding surface of the pedestal has the highest elevation of the substrate and comprises a plurality of first metallic interconnect interfaces adjacent to a dielectric material; and
an integrated circuit (IC) die hybrid bonded exclusively to the bonding surface of the pedestal, wherein:
a bonding surface of the IC die comprises a plurality of second metallic interconnect interfaces adjacent to another dielectric material;
each of the second metallic interconnect interfaces is in direct contact with a corresponding one of the first metallic interconnect interfaces and the adjacent dielectric materials are also in direct contact with each other; and
a periphery of the IC die beyond the bonding surface of the IC die overhangs the recessed surface on all sides of the pedestal.
2 . The apparatus of claim 1 , further comprising a package dielectric over and adjacent to a sidewall of the IC die, and between the recessed surface and the periphery of the IC die.
3 . The apparatus of claim 1 , wherein the periphery of the IC die extends at least 2 μm beyond at least one side of the pedestal.
4 . The apparatus of claim 3 , wherein a sidewall of the pedestal has a height from the bonding surface of the pedestal to the recessed surface that is at least equal to a length that the periphery of the IC die overhangs all sides of the pedestal.
5 . The apparatus of claim 1 , wherein the first metallic interconnect interfaces comprise copper and wherein the second metallic interconnect interfaces comprise copper.
6 . The apparatus of claim 3 , wherein the IC die extends at least 10 μm beyond at least one side of the pedestal.
7 . The apparatus of claim 6 , wherein the IC die extends at least 15 μm beyond at least one side of the pedestal.
8 . A system, comprising:
a substrate, wherein a highest elevation of the substrate comprises a bonding surface of a first pedestal and a bonding surface of a second pedestal, and wherein a recessed surface of the substrate surrounds a perimeter of each of the first and second pedestals, and wherein the bonding surface of each of the first and second pedestals comprises a plurality of first metallic interconnect interfaces and a first dielectric material; and
first and second integrated circuit (IC) dies, each one of the IC dies hybrid bonded exclusively to one of the bonding surfaces of a corresponding single one of the first and second pedestals, wherein a bonding surface of each of the first and second IC dies comprises a plurality of second metallic interconnect interfaces in direct contact with the first metallic interconnect interfaces and a second dielectric material in direct contact with the first dielectric material, wherein a peripheral portion of the first IC die beyond the bonding surface of the first IC die extends beyond a sidewall of the first pedestal and overhangs the recessed surface on all sides of the first pedestal, and wherein a peripheral portion of the second IC die beyond the bonding surface of the second IC die extends beyond a sidewall of the second pedestal and overhangs the recessed surface on all sides of the second pedestal.
9 . The system of claim 8 , wherein the first and second pedestals are spaced apart by a distance and the recessed surface spans an entirety of the distance.
10 . The system of claim 8 , further comprising:
a host component coupled to the substrate; and
a power supply coupled to the substrate through the host component.
11 . The system of claim 8 , wherein a lateral width of the recessed surface between the first and second pedestals is not more than 40 μm.
12 . The system of claim 11 , wherein a lateral distance between the first and second IC dies is at least 2 μm.
13 . The system of claim 8 , further comprising a package dielectric over and adjacent to the first and second IC dies, and between the recessed surface and the peripheral portion of each of the first and second IC dies.
14 . The system of claim 8 , wherein the first metallic interconnect interfaces of each of the first IC die and the second IC die comprise copper and wherein the second metallic interconnect interfaces of each of the first pedestal and the second pedestal comprise copper.
15 . The system of claim 12 , wherein the first IC die extends at least 10 μm beyond at least one side of the first pedestal, and wherein the second IC die extends at least 10 μm beyond at least one side of the second pedestal.
16 . The system of claim 15 , wherein the first IC die extends at least 15 μm beyond at least one side of the first pedestal, and wherein the second IC die extends at least 15 μm beyond at least one side of the second pedestal.