Package structure and method for manufacturing same, semiconductor device

Inventors: Kai Tian (Hefei, CN); Liang Chen (Hefei, CN); Mingxing Zuo (Hefei, CN)

Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.

H10W72/90 H10W72/019 H10W70/05 H10W70/652 H10W70/66 H10W72/01961 H10W72/932 H10W72/942 H10W72/952 H10W72/967

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Quick Facts

Patent No.: US 12702045
App. No.: 17/939,045
Granted: Aug 4, 2026
Kind: B2

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Abstract

A packaging structure, a method for manufacturing the same and a semiconductor device are provided. The packaging structure includes a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure, and an insulating layer covering and exposing part of the redistribution layer. The exposed part of the redistribution layer includes at least one first pad. The first pad includes a first area and a second area arranged continuously. The first area is configured for testing. The second area is configured for performing functional interaction corresponding to content of the test.

Claims (38)

1 . A package structure, comprising:

a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure; and

an insulating layer covering the redistribution layer and exposing part of the redistribution layer;

wherein the exposed part of the redistribution layer comprises at least one first pad, the first pad comprises a first area and a second area arranged continuously, the first area is configured to perform a probe card sticking test, and the second area is configured for leading out bonding wires on the first pad;

further comprising: a plurality of second pads, which are composed of part of the redistribution layer exposed by the insulating layer and are configured to perform the test or performing the functional interaction corresponding to the content of the test,

wherein at least part of the plurality of the second pads and the at least one first pad are arranged side by side along a first direction, the first direction is perpendicular to a direction from the first area to the second area, and an area of each first pad is larger than an area of each of the second pads;

wherein the first pad and the second pads both have a strip shape, a width of the first pad along the first direction is same as a width of the second pads along the first direction, spacing distances between any two adjacent pads are equal, and all pads arranged side by side along the first direction are flush at one end;

wherein a number of the at least one first pad is multiple, at least part of the first pads are arranged side by side along the first direction near a first edge of the semiconductor functional structure, and at least part of the second pads are arranged side by side along the first direction on both sides of the at least part of the first pads;

wherein a first number of the second pads are provided on a first side of the at least part of the first pads, a second number of the second pads are provided on a second side of the at least part of the first pads, and the first number is different from the second number.

2 . The package structure according to claim 1 , wherein at least two of the second pads are provided on each side of the at least part of the first pads.

3 . The package structure according to claim 1 , wherein

part of the second pads are arranged side by side along the first direction on both sides of the at least part of the first pad, and another part of the second pads are arranged side by side along a second direction near a second edge of the semiconductor functional structure, the second direction is perpendicular to the first direction, and the first edge and the second edge are two opposite edges of the semiconductor functional structure.

4 . The package structure according to claim 1 , wherein a number of at least one the first pad is multiple, part of the first pads are arranged side by side along the first direction near a first edge of the semiconductor functional structure, and another part of the first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure, part of the second pads are arranged side by side along the first direction on both sides of the part of the first pads, and another part of the second pads are arranged side by side along the first direction on both sides of the another part of the first pads, and the first edge and the second edge are two opposite edges of the semiconductor functional structure.

5 . The package structure according to claim 4 , wherein an arrangement of the first pads and the second pads near the first edge of the semiconductor functional structure is symmetrical with an arrangement of the first pads and the second pads near the second edge of the semiconductor functional structure.

6 . The package structure according to claim 1 , wherein all of the pads arranged side by side along the first direction are flush at one end near an edge of the semiconductor functional structure;

the first area is located at an end of each first pad near the edge of the semiconductor functional structure, and the second area is located at an end of each of the first pads away from the edge of the semiconductor functional structure.

7 . A semiconductor device, comprising a semiconductor functional structure and a package structure according to claim 1 .

8 . A semiconductor device, comprising a semiconductor functional structure and a package structure according to claim 2 .

9 . A semiconductor device, comprising a semiconductor functional structure and a package structure according to claim 3 .

10 . A semiconductor device, comprising a semiconductor functional structure and a package structure according to claim 4 .

11 . A semiconductor device, comprising a semiconductor functional structure and a package structure according to claim 5 .

12 . A package structure, comprising:

a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure; and

an insulating layer covering the redistribution layer and exposing part of the redistribution layer;

wherein part of the second pads are arranged side by side along the first direction on both sides of the at least part of the first pad, and another part of the second pads are arranged side by side along a second direction near a second edge of the semiconductor functional structure, the second direction is perpendicular to the first direction, and the first edge and the second edge are two opposite edges of the semiconductor functional structure.

13 . A package structure, comprising:

a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure; and

an insulating layer covering the redistribution layer and exposing part of the redistribution layer;

wherein a number of at least one the first pad is multiple, part of the first pads are arranged side by side along the first direction near a first edge of the semiconductor functional structure, and another part of the first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure, part of the second pads are arranged side by side along the first direction on both sides of the part of the first pads, and another part of the second pads are arranged side by side along the first direction on both sides of the another part of the first pads, and the first edge and the second edge are two opposite edges of the semiconductor functional structure.