IP Library › Granted Patent US 12702048
Granted Patent B2
US 12702048 · App. 18/144,578 · Granted Aug 4, 2026

Encapsulated package with exposed electrically conductive structures and sidewall recess

Inventors: Chee Hong Lee (Paya Rumput, MY); Soon Lock Goh (Malacca, MY); Chai Chee Lee (Melaka, MY); Swee Kah Lee (Melaka, MY); Luay Kuan Ong (Melaka, MY); Chee Voon Tan (Seremban, MY)
Assignee: Infineon Technologies AG
H10W74/111H10W70/424H10W70/481H10W74/016H10W90/811
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Quick Facts
Patent No.
US 12702048
App. No.
18/144,578
Granted
Aug 4, 2026
Kind
B2
Abstract

A package is disclosed. In one example, the package includes an electronic component and an encapsulant encapsulating at least part of the electronic component. A first electrically conductive structure is arranged on one side of the electronic component, a second electrically conductive structure arranged on an opposing other side of the electronic component and being electrically coupled with the electronic component, and at least one sidewall recess at the encapsulant. The first electrically conductive structure and the second electrically conductive structure are configured to be at different electric potentials during operation of the package. The first electrically conductive structure and the second electrically conductive structure are exposed at opposing main surfaces of the encapsulant.

Claims (38)

1 . A package, comprising:

an electronic component;

an encapsulant encapsulating at least part of the electronic component;

a first electrically conductive structure arranged on one side of the electronic component;

a second electrically conductive structure arranged on an opposing other side of the electronic component and being electrically coupled with the electronic component; and

at least one sidewall recess at the encapsulant, wherein the sidewall recess extends up to only one of two opposing main surfaces of the encapsulant, and wherein the sidewall recess exposes a sidewall portion of the first electrically conductive structure; and

wherein the first electrically conductive structure and the second electrically conductive structure are configured to be at different electric potentials during operation of the package, and wherein the first electrically conductive structure and the second electrically conductive structure are exposed at opposing main surfaces of the encapsulant.

2 . The package according to claim 1 , wherein the at least one sidewall recess comprises at least two sidewall recesses arranged at opposing sidewalls of the encapsulant.

3 . The package according to claim 1 , wherein the at least one sidewall recess comprises at least two sidewall recesses arranged mutually spaced at the same sidewall of the encapsulant.

4 . The package according to claim 1 , comprising at least one of the following features:

wherein the package is locally thinned at the at least one sidewall recess to a thickness of not more than 4 mm, in particular to a thickness in a range from 0.125 mm to 1 mm;

wherein a lateral depth of the at least one sidewall recess is not more than 4 mm, in particular is in a range from 0.1 mm to 4 mm.

5 . The package according to claim 1 , comprising at least one electrically conductive coupling element coupling the electronic component with the second electrically conductive structure.

6 . The package according to claim 1 , comprising one of the following features:

wherein the first electrically conductive structure comprises a carrier;

wherein the first electrically conductive structure comprises a clip.

7 . The package according to claim 1 , comprising at least one of the following features:

wherein the second electrically conductive structure comprises at least one plated structure;

wherein the encapsulant is a plateable mold compound.

8 . The package according to claim 1 , wherein an exposed portion of the first electrically conductive structure and/or an exposed portion of the second electrically conductive structure comprises a surface finish.

9 . The package according to claim 1 , comprising one of the following features:

wherein the package is tie bar-less;

comprising at least one tie bar stub being integrally formed with the first electrically conductive structure and being exposed at the at least one sidewall recess.

10 . The package according to claim 1 , wherein the electronic component comprises a transistor chip.

11 . The package according to claim 10 , wherein the first electrically conductive structure forms a source terminal and the second electrically conductive structure forms a drain terminal of the transistor chip, wherein in particular the second electrically conductive structure additionally forms a gate terminal of the transistor chip.

12 . The package according to claim 10 , comprising a further transistor chip being at least partially encapsulated by the encapsulant.

13 . The package according to claim 11 , wherein the second electrically conductive structure additionally forms a source terminal of the further transistor chip.

14 . The package according to claim 10 , wherein the transistor chip and the further transistor chip have a common gate terminal and/or have a common drain terminal.

15 . The package according to claim 1 , comprising one of the following features:

wherein the first electrically conductive structure is electrically coupled with the electronic component;

wherein the first electrically conductive structure is not electrically coupled with the electronic component.

16 . A method of manufacturing a package, the method comprising:

encapsulating at least part of an electronic component by an encapsulant;

arranging a first electrically conductive structure on one side of the electronic component;

arranging a second electrically conductive structure on an opposing other side of the electronic component so as to be electrically coupled with the electronic component, wherein the first electrically conductive structure and the second electrically conductive structure are configured to be at different electric potentials during operation of the package, and wherein the first electrically conductive structure and the second electrically conductive structure are exposed at opposing main surfaces of the encapsulant; and

forming at least one sidewall recess in the encapsulant which is unfilled and exposed to an exterior of the package.

17 . The method according to claim 16 , wherein the method comprises forming the at least one sidewall recess by etching.

18 . The method according to claim 16 , wherein the method comprises forming the at least one sidewall recess by removing material of a tie bar temporarily interconnecting the first electrically conductive structure with a further electrically conductive structure during part of the method of manufacturing the package.