Semiconductor structure and method of fabricating same
A method of fabricating a semiconductor device that includes a first die component and at least one second die component. The first die component includes a substrate, a dielectric layer on the substrate, and one or more metal pads positioned on the dielectric layer. The first die component further includes a passivation/bond film layer that is formed over the one or more metal pads, and one or more bond pad vias that extend through the passivation/bond film layer and contact one or more metal pads. The at least one second die component is bonded to the first die component and includes a substrate, and one or more through silicon vias, with the one or more through silicon vias contacting the one or more bond pad vias.
1 . A method of fabricating a semiconductor device comprising:
forming an interconnection metal structure within a dielectric layer formed on an integrated circuit (IC) substrate;
forming a metal-insulator-metal (MIM) component within the dielectric layer, the MIM component extending over a first portion of the interconnection metal structure;
forming at least one metal BPV landing pad on the dielectric layer, the at least one metal BPV landing pad extending over the MIM component and the at least one metal BPV landing pad extending over a second portion of the interconnection metal structure;
forming an etch stop layer on the at least one BPV landing metal pad;
depositing at least one of a passivation layer or bond film on the etch stop layer;
patterning a photoresist layer on the at least one passivation layer or bond film, wherein at least one via region is formed in the photoresist layer proximal to the at least one metal BPV landing pad;
etching the at least one passivation layer or bond film to remove a portion thereof in the at least one via region and exposing a portion of the at least one metal BPV landing pad; and
forming at least one bond pad via through the at least one passivation layer or bond film in the at least one via region, the at least one bond pad via contacting the exposed portion of the at least one metal BPV landing pad,
wherein the MIM component is laterally offset from the at least one bond pad via.
2 . The method of claim 1 , wherein the step of forming the at least one bond pad via further comprises:
depositing a conductive layer on the photoresist layer, wherein the conductive layer extends through the at least one via region to contact the at least one metal BPV landing pad, forming the at least one bond pad via therein; and
performing chemical mechanical polishing to remove a portion of the conductive layer and a portion of the at least one passivation layer or bond film.
3 . The method of claim 1 , wherein the MIM component is a super high density metal-insulator-metal component, and the MIM component is laterally offset from the at least one bond pad via by a first distance D1 associated with a keep out zone (KOZ), the KOZ defined as a region around the at least one via region, adjacent to the first portion of the interconnection metal structure, and extending over the second portion of the interconnection metal structure.
4 . The method of claim 3 , wherein the KOZ is defined between an edge of the at least one super high-density metal-insulator-metal component and an edge of the at least one bond pad via.
5 . The method of claim 4 , wherein the KOZ has a range of greater than or equal to 5 μm.
6 . The method of 3 , wherein the at least one bond pad via has a metal BPV landing pad recess corresponding to a depth D2 into the at least one metal BPV landing pad into which the at least one bond pad via extends, wherein the metal BPV landing pad recess depth D2 is in the range of about 0 μm to about 0.1 μm.
7 . The method of 3 , wherein the at least one bond pad via has a metal BPV landing pad lateral recess corresponding to a distance D3 of bond pad material extending perpendicularly out from an edge of the at least one bond pad via, wherein the metal BPV landing pad lateral recess distance D3 is in the range of about 0 μm to about 0.1 μm.
8 . The method of claim 3 , wherein the dielectric layer on the interconnection metal structure includes at least one top metal component, and wherein the at least one metal BPV landing pad extends over the at least one top metal component.
9 . A method of fabricating a semiconductor device, comprising:
forming a first die component comprising:
forming an interconnection metal structure within a dielectric layer formed on an integrated circuit (IC) substrate;
forming a metal-insulator-metal (MIM) component within the dielectric layer, the MIM component extending over a first portion of the interconnection metal structure;
forming a metal BPV landing pad on the dielectric layer, the metal BPV landing pad extending over the MIM component and the metal BPV landing pad extending over a second portion of the interconnection metal structure;
depositing at least one of a passivation layer or bond film over the metal BPV landing pad; and
forming at least one bond pad via through the at least one of the passivation layer or bond film, the at least one bond pad via formed on at least one the metal BPV landing pad,
wherein the MIM component is laterally offset from the at least one bond pad via;
forming a second die component comprising:
forming at least one through silicon via through a second die substrate; and
bonding the first die component to the second die component, wherein the at least one bond pad via is contacting the at least one through silicon via.
10 . The method of claim 9 , wherein wherein the MIM component is laterally offset from the at least one bond pad via by a first distance D1 associated with a keep out zone (KOZ), the KOZ defined as a region around the at least one bond pad via region, adjacent to the first portion of the interconnection metal structure, and extending over the second portion of the interconnection metal structure.
11 . The method of claim 10 , wherein the KOZ is defined between an edge of the at least one super high-density metal-insulator-metal component and an edge of the at least one bond pad via.
12 . The method of claim 11 , wherein the KOZ has a range of greater than or equal to 5 μm.
13 . The method of claim 10 , wherein the at least one bond pad via has a metal BPV landing pad recess depth D2 in the range of about 0 μm to about 0.1 μm.
14 . The method of claim 10 , wherein the at least one bond pad via has a metal BPV landing pad lateral recess distance D3 in the range of about 0 μm to about 0.1 μm.
15 . A semiconductor device comprising:
a first die component comprising:
a substrate,
a dielectric layer disposed on the substrate,
an interconnection metal structure formed within the dielectric layer,
a metal-insulator-metal (MIM) component formed within the dielectric layer, the MIM component extending over a first portion of the interconnection metal structure;
a metal BPV landing pad disposed over the interconnection metal structure and disposed on the dielectric layer, the metal BPV landing pad extending over the MIM component and the metal BPV landing pad extending over a second portion of the interconnection metal structure,
a passivation/bond film layer formed over the metal BPV landing pad, and
a bond pad via, the bond pad via extending through the passivation/bond film layer and contacting the metal BPV landing pad,
wherein the MIM component is laterally offset from the bond pad via; and
at least one second die component bonded to the first die component, the second die component comprising:
a substrate, and
at least one through silicon via;
wherein the at least one bond pad via contacts the at least one through silicon via.
16 . The semiconductor device of claim 15 , wherein the MIM component is a super high density metal-insulator-metal component and the super high-density metal-insulator-metal component is disposed in the dielectric layer in proximity to the metal BPV landing pad.
17 . The semiconductor device of claim 16 , wherein the MIM component is laterally offset from the bond pad via by a first distance D1 associated with a keep out zone (KOZ), the KOZ defined as a region around the bond pad via, adjacent to the first portion of the interconnection metal structure, and extending over the second portion of the interconnection metal structure, and the KOZ is further defined between an edge of the super high-density metal-insulator-metal component and an edge of the bond pad via.
18 . The semiconductor device of claim 17 , wherein the KOZ has a range of greater than or equal to 5 μm.
19 . The semiconductor device of claim 15 , wherein the bond pad via has a metal BPV landing pad recess in the range of about 0 μm to about 0.1 μm.
20 . The semiconductor device of claim 15 , wherein the bond pad via has a metal BPV landing pad lateral recess in the range of about 0 μm to about 0.1 μm.