Frame edge reinforcement structure for package structures and methods of using the same
A device structure includes: an interposer including interposer dielectric material layers having formed therein interposer metal interconnect structures and die-side interposer bonding pads; at least one semiconductor die having formed therein in-die bonding pads that are bonded to a respective one of the die-side interposer bonding pads by metal-to-metal bonding; and a composite die frame laterally surrounding the at least one semiconductor die. The composite die frame includes a molding compound die frame portion including a molding compound material and frame edge reinforcement structures located at corners of the composite die frame and including a material having a lower coefficient of thermal expansion at 20 degrees Celsius than the molding compound material.
1 . A device structure comprising:
an interposer comprising interposer dielectric material layers having formed therein interposer metal interconnect structures and die-side interposer bonding pads;
at least one semiconductor die each comprising a respective set of semiconductor devices and respective in-die dielectric material layers having formed therein in-die metal interconnect structures and in-die bonding pads, wherein the in-die bonding pads are bonded to a respective one of the die-side interposer bonding pads by metal-to-metal bonding; and
a composite die frame laterally surrounding the at least one semiconductor die and contacting a horizontal surface of one of the interposer dielectric material layers, wherein the composite die frame comprises a molding compound die frame portion comprising a molding compound material and frame edge reinforcement structures located at corners of the composite die frame and comprising a material having a lower coefficient of thermal expansion at 20 degrees Celsius than the molding compound material.
2 . The device structure of claim 1 , wherein one of the frame edge reinforcement structures comprises at least one outer sidewall surface that is physically exposed to a gas-phase ambient.
3 . The device structure of claim 1 , wherein one of the frame edge reinforcement structures comprises at least one inner sidewall surface that is in direct contact with one of the at least one semiconductor die.
4 . The device structure of claim 1 , wherein one of the frame edge reinforcement structures comprises a proximal horizontal surface in direct contact with a horizontal surface of the interposer dielectric material layers.
5 . The device structure of claim 1 , wherein one of the frame edge reinforcement structures comprises a distal horizontal surface in direct contact with a horizontal surface of the molding compound die frame portion.
6 . The device structure of claim 1 , wherein one of the frame edge reinforcement structures comprises a pair of vertically-extending sidewalls in direct contact with vertical surfaces of the molding compound die frame portion.
7 . The device structure of claim 1 , wherein each of the at least one semiconductor die comprises a respective topmost in-die dielectric material layer that is bonded to a topmost interposer dielectric material layer selected from the interposer dielectric material layers via dielectric-to-dielectric bonding.
8 . The device structure of claim 1 , wherein:
the at least one semiconductor die comprises a plurality of semiconductor dies that are laterally spaced apart from one another by the molding compound die frame portion; and
the frame edge reinforcement structures are located entirely outside areas of gaps between neighboring pairs of the plurality of semiconductor dies in a plan view.
9 . The device structure of claim 1 , wherein the frame edge reinforcement structures have a same height as each of the at least one semiconductor die.
10 . The device structure of claim 1 , wherein the frame edge reinforcement structures have a height that is less than a height of the at least one semiconductor die.
11 . A device structure comprising:
a silicon interposer comprising a silicon substrate, through-silicon via structures provided within the silicon substrate, and interposer dielectric material layers having formed therein interposer metal interconnect structures and die-side interposer bonding pads;
at least one semiconductor die comprising in-die bonding pads that are bonded to the die-side interposer bonding pads; and
a composite die frame laterally surrounding the at least one semiconductor die and including a molding compound die frame portion comprising a molding compound material and frame edge reinforcement structures located at corners of the composite die frame and comprising a material having a lower coefficient of thermal expansion at 20 degrees Celsius than the molding compound material.
12 . The device structure of claim 11 , wherein the frame edge reinforcement structures comprise a material selected from an additional molding compound material, a die attachment film, an epoxy material, an underfill material, and a semiconductor material.
13 . The device structure of claim 11 , wherein at least one of the frame edge reinforcement structures has an L-shaped horizontal cross-sectional shape.
14 . The device structure of claim 11 , wherein at least one of the frame edge reinforcement structures has a rectangular horizontal cross-sectional shape.
15 . The device structure of claim 11 , wherein each of the at least one semiconductor die comprises a respective set of semiconductor devices and respective in-die dielectric material layers having formed therein in-die metal interconnect structures and in-die bonding pads, wherein the in-die bonding pads are bonded to a respective one of the die-side interposer bonding pads by metal-to-metal bonding.
16 . A method of forming a device structure, the method comprising:
providing a structure comprising a silicon interposer including a portion of a silicon substrate, through-silicon via structures provided within the silicon substrate, and interposer dielectric material layers having formed therein interposer metal interconnect structures and die-side interposer bonding pads;
bonding at least one semiconductor die comprising in-die bonding pads to the silicon interposer such that the in-die bonding pads are bonded to the die-side interposer bonding pads; and
forming a composite die frame around the at least one semiconductor die, wherein the composite die frame includes a molding compound die frame portion comprising a molding compound material and frame edge reinforcement structures located at corners of the composite die frame and comprising a material having a lower coefficient of thermal expansion at 20 degrees Celsius than the molding compound material.
17 . The method of claim 16 , wherein:
the structure comprise a two-dimensional array of silicon interposers including the silicon interposer; and
the method comprises disposing in-process frame edge reinforcement structures around the at least one semiconductor die and dicing the in-process frame edge reinforcement structures and the silicon substrate, wherein diced portions of the in-process frame edge reinforcement structures comprise the frame edge reinforcement structures.
18 . The method of claim 17 , wherein the in-process frame edge reinforcement structures are disposed directly on a top surface of the interposer dielectric material layers.
19 . The method of claim 17 , further comprising forming a molding compound material layer comprising the molding compound material around the at least one semiconductor die and the in-process frame edge reinforcement structure, wherein the molding compound die frame portion comprises a diced portion of the molding compound material.
20 . The method of claim 16 , wherein:
the in-die bonding pads are bonded to the die-side interposer bonding pads by metal-to-metal bonding; and
each of the at least one semiconductor die comprises a respective in-die dielectric material layer that is bonded to the a topmost interposer dielectric layer selected from the interposer dielectric material layers by dielectric-to-dielectric bonding,
forming one or more of the first gate dielectric layer and the second gate dielectric layer to comprise at least one of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, or hafnium dioxide-alumina;
forming one or more of the first source electrode, the second source electrode, or the shared drain electrode to comprise one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, or Al; and
forming a further interlayer dielectric layer that partially surrounds the gate electrode.