Glass core patches embedded in encapsulating material for packaged integrated circuit devices
An electronic device comprises a mold layer that includes multiple integrated circuit (IC) dice having contact pads, a glass core patch embedded in encapsulating material that surrounds the top, bottom, and sides of the glass core patch, and a first redistribution layer arranged between the first mold layer and the glass core patch. The first redistribution layer includes electrically conductive interconnect that electrically connects one or more contact pads of the IC dice to the glass core patch.
1 . An electronic device, comprising:
a device layer that comprises multiple integrated circuit (IC) dice embedded in a first mold material, the IC dice each having contact pads;
a core layer that comprises a glass core patch embedded in an encapsulating material that surrounds a top, a bottom, and sides of the glass core patch, the glass core patch comprising through glass vias (TGVs), and the encapsulating material comprising through layer vias; and
a first redistribution layer that comprises electrically conductive interconnects and a discrete silicon interposer embedded in dielectric material that surrounds a top, a bottom, and sides of the discrete silicon interposer, wherein the device layer is on the first redistribution layer and the first redistribution layer is on the encapsulating material of the core layer, the electrically conductive interconnects electrically connect first contact pads of the IC dice to the glass core patch, an entirety of the discrete silicon interposer is above an entirety of the glass core patch, and the discrete silicon interposer electrically connects at least two of the IC dice.
2 . The electronic device of claim 1 , wherein a first through layer via of the through layer vias is connected to a first end of a first TGV of the TGVs, and a second through layer via of the through layer vias is connected to a second end of the first TGV.
3 . The electronic device of claim 1 , further comprising:
a second redistribution layer opposite the glass core patch from the first redistribution layer.
4 . The electronic device of claim 1 , wherein the electrically conductive interconnects are laterally adjacent the discrete silicon interposer.
5 . The electronic device of claim 1 , wherein a portion of the encapsulating material and a portion of the dielectric material are between the top of the glass core patch and the bottom of the discrete silicon interposer.
6 . The electronic device of claim 1 , wherein the encapsulating material comprises at least one of a second mold material or a dielectric material.
7 . The electronic device of claim 1 , wherein the glass core patch comprises silicate glass or fused silica glass, and the glass core patch has a thickness of not more than 500 microns.
8 . The electronic device of claim 1 , wherein the discrete silicon interposer electrically connects second contact pads of the IC dice to the glass core patch.
9 . The electronic device of claim 1 , wherein the encapsulating material comprises saw marks.
10 . The electronic device of claim 1 , further comprising:
an antenna coupled to one or more of the IC dice.
11 . An electronic device, comprising:
a device layer comprising multiple integrated circuit (IC) dice in a first mold material, the IC dice each having contact pads;
a core layer comprising a glass core patch in an encapsulating material that surrounds a top, a bottom, and sides of the glass core patch, the glass core patch comprising through glass vias (TGVs), and the encapsulating material comprising through layer vias; and
a first redistribution layer comprising interconnects and a discrete silicon die-to-die bridge in dielectric material that surrounds a top, a bottom, and sides of the discrete silicon die-to-die bridge, wherein the device layer is on the first redistribution layer and the first redistribution layer is on the encapsulating material of the core layer, the interconnects connect first contact pads of the IC dice to the glass core patch, an entirety of the discrete silicon die-to-die bridge is above an entirety of the glass core patch, and the discrete silicon die-to-die bridge connects at least two of the IC dice.
12 . The electronic device of claim 11 , wherein a first through layer via of the through layer vias is connected to a first end of a first TGV of the TGVs, and a second through layer via of the through layer vias is connected to a second end of the first TGV.
13 . The electronic device of claim 11 , further comprising:
a second redistribution layer opposite the glass core patch from the first redistribution layer.
14 . The electronic device of claim 11 , wherein the interconnects are laterally adjacent the discrete silicon die-to-die bridge.
15 . The electronic device of claim 11 , wherein a portion of the encapsulating material and a portion of the dielectric material are between the top of the glass core patch and the bottom of the discrete silicon die-to-die bridge.
16 . The electronic device of claim 11 , wherein the encapsulating material comprises at least one of a second mold material or a dielectric material.
17 . The electronic device of claim 11 , wherein the glass core patch comprises silicate glass or fused silica glass, and the glass core patch has a thickness of not more than 500 microns.
18 . The electronic device of claim 11 , wherein the discrete silicon die-to-die bridge connects second contact pads of the IC dice to the glass core patch.
19 . The electronic device of claim 11 , wherein the encapsulating material comprises saw marks.
20 . The electronic device of claim 11 , further comprising:
an antenna coupled to one or more of the IC dice.