Three-dimensional semiconductor package having a stacked passive device
A three-dimensional semiconductor package assembly includes a die. The die includes a plurality of through silicon vias (TSVs). The TSVs includes a first TSV and a second TSV. The first TSV supplies power from an active surface of the die to a back surface of the die. The assembly also includes a passive device coupled to the back surface of the die such that conductive contacts of the passive device electrically interface with the TSVs. The first passive device receives power through the first TSV and supplies power to the first die through the second TSV.
1 . A semiconductor package assembly comprising:
a first die including a first TSV (Through Silicon Via) and a second TSV, wherein the first TSV supplies power received at a first surface of the first die to a second surface of the first die;
a first passive device coupled to the second surface of the first die such that conductive contacts of the first passive device electrically interface with the first and second TSV, wherein the first passive device receives power supplied through the first TSV and supplies power to the first die through the second TSV, wherein the second TSV terminates at a power bus positioned within the first die between the first surface and the second surface; and
a second die coupled to the second surface of the first die such that conductive contacts of the second die electrically interface with a third TSV and a fourth TSV included in the first die, wherein the third TSV terminates at the power bus, and wherein the second die receives power supplied from the first passive device through a pathway that sequentially includes the second TSV, the power bus, and the third TSV.
2 . The semiconductor package assembly of claim 1 , wherein the pathway configured to provide power to the second die sequentially includes the first TSV, the first passive device, the second TSV, the power bus, and the third TSV.
3 . The semiconductor package assembly of claim 1 further comprising:
a second die including a third TSV and a fourth TSV, wherein the third TSV supplies power received at a first surface of the second die to a second surface of the second die;
a second passive device coupled to the second surface of the second die such that conductive contacts of the second passive device electrically interface with the third TSV and fourth TSV in the second die, wherein the second passive device receives power supplied through the third TSV and supplies power to the second die through the fourth TSV, wherein the fourth TSV terminates at a power bus within the second die;
a mold layer including encapsulant material partially encapsulating the first die, the second die, the first passive device, and the second passive device; and
a redistribution layer structure fabricated on the first surface of the first die, the first surface of the second die, and coplanar surfaces of the mold material.
4 . The semiconductor package assembly of claim 3 , wherein:
the first passive device is coupled to an area of the second surface of the first die opposite a PHY (‘Physical Device’) region of the first surface of the first die; and
the second passive device is coupled to an area of the second surface of the second die opposite a PHY region of the first surface of the second die.
5 . The semiconductor package assembly of claim 1 , wherein the first passive device is a chip capacitor.
6 . The semiconductor package of claim 1 , wherein the first passive device includes a decoupling capacitor.
7 . The semiconductor package of claim 6 , wherein the first passive device stores energy in the decoupling capacitor using power received through the first TSV, and wherein the first passive device supplies power to the first die through the second TSV using the energy stored in the decoupling capacitor.
8 . The semiconductor package of claim 1 , wherein the first passive device stores energy in a capacitor using power received through the first TSV, and wherein the first passive device supplies power to the first die through the second TSV using the energy stored in the capacitor.
9 . The semiconductor package of claim 1 , wherein the second TSV terminates at the power bus positioned within the first die between the first surface and the second surface at a device layer of the first die.
10 . The semiconductor package of claim 1 , wherein the first passive device is bonded to the second surface of the first die by microbumps.
11 . The semiconductor package of claim 1 , wherein the first passive device is bonded to the second surface of the first die using a hybrid bonding process.
12 . An apparatus comprising:
a substrate; and
a semiconductor package assembly mounted on the substrate, the semiconductor package assembly comprising:
a first die including a first TSV (Through Silicon Via) and a second TSV, wherein the first TSV supplies power received from the substrate at an first surface of the first die to a second surface of the first die;
a first passive device coupled to the second surface of the first die such that conductive contacts of the first passive device electrically interface with the first TSV and second TSV, wherein the first passive device receives power through the first TSV and supplies power to the first die through the second TSV, wherein the second TSV terminates at a power bus positioned within the first die between the first surface and the second surface; and
a second die coupled to the second surface of the first die such that conductive contacts of the second die electrically interface with a third TSV and a fourth TSV included in the first die, wherein the third TSV terminates at the power bus, and wherein the second die receives power supplied from the first passive device through a pathway that sequentially includes the second TSV, the power bus, and the third TSV.
13 . The apparatus of claim 12 , wherein the pathway configured to provide power to the second die sequentially includes the first TSV, the first passive device, the second TSV, the power bus, and the third TSV.
14 . The apparatus of claim 12 , wherein the semiconductor package assembly includes:
a second die including a third TSV and a fourth TSV, wherein the third TSV supplies power from an first surface of the second die to a second surface of the second die;
a second passive device coupled to the second surface of the second die such that conductive contacts of the second passive device electrically interface with the third TSV and the fourth TSV, wherein the second passive device receives power through the third TSV and supplies power to the second die through the fourth TSV, wherein the fourth TSV terminates at a power bus within the second die;
a mold layer including encapsulant material partially encapsulating the first die, the second die, the first passive device, and the second passive device; and
a redistribution layer structure fabricated on the first surface of the first die, the first surface of the second die, and coplanar surfaces of the mold material.
15 . The apparatus of claim 14 , wherein:
the first passive device is coupled to an area of the second surface of the first die opposite a PHY (‘Physical Device’) region of the first surface of the first die; and
the second passive device is coupled to an area of the second surface of the second die opposite a PHY region of the first surface of the second die.
16 . The apparatus of claim 12 , wherein the first passive device is a chip capacitor.
17 . The apparatus of claim 12 , wherein the first passive device includes a decoupling capacitor.
18 . The apparatus of claim 17 , wherein the first passive device stores energy in the decoupling capacitor using power received through the first TSV, and wherein the first passive device supplies power to the first die through the second TSV using the energy stored in the decoupling capacitor.
19 . The apparatus of claim 12 , wherein the first passive device is bonded to the second surface of the first die by microbumps.
20 . The apparatus of claim 12 , wherein the first passive device is bonded to the second surface of the first die using a hybrid bonding process.