Memory on package (MOP) with reverse CAMM (compression attached memory module) and CMT connector
Memory on Package (MOP) apparatus with reverse CAMM (Compression Attached Memory Module) and compression mount technology (CMT) connector(s). The MOP includes a first (MOP) substrate to which one or more CPUs, SoC, and XPUs that is operatively coupled to one or more CAMMs with a CMT connector(s) disposed between an array of CMT contact pads on the CAMM substrate and an array of CMT contact pad on the substrate. The one or more CAMMs are include multiple memory chips or packages such as LP DDR chips or DDR (S)DRAM chips/packages mounted to an underside of the CAMM substrate via signal coupling means such as a ball grid array (BGA), where the CAMM orientation is inverted such that the memory chips/packages are disposed downward, resulting in a reduced Z-height of the MOP. A MOP may include two CAMMs with a respective CMT connector disposed between the CAMM substrates and the MOP substrate.
1 . A memory on package (MOP), comprising:
a first substrate having one or more of a Central Processing Unit (CPU), System on a Chip (SoC) and other processing unit (XPU) mounted to a topside thereof and including one or more first arrays of compression mount technology (CMT) contacts pads disposed on the topside having and means for coupling signals for at least one or the CPU, SoC, and XPU to the one or more first arrays of CMT contact pads;
a Compression Attached Memory Module (CAMM) comprising,
a second substrate including a one or more second arrays of compression mount technology (CMT) contact pads disposed on a first side, plurality of first signal coupling arrays comprising first arrays of signal coupling means disposed on the first side of the second substate and including wiring connecting CMT contact pads to signal coupling means in the plurality of first signal coupling arrays; and
multiple memory chips or packages, each comprising a second signal coupling array comprising a second array of signal coupling means, wherein the signal coupling means in the second signal coupling array for a given memory chip or package are coupled to signal coupling means in a respective first signal coupling array on the second substrate; and
a CMT connector disposed between the first substrate and the second substrate, wherein the CMT connector includes an array of spring-loaded contacts or pins in contact with CMT contact pads in the one or more first arrays and one or more second arrays of CMT contact pads.
2 . The MOP of claim 1 , wherein the one or more second signal coupling arrays comprise one or more ball grid arrays (BGAs).
3 . The MOP of claim 1 , wherein the plurality of memory chips includes Low Power (LP) Double Data Rate (DDR) memory chips.
4 . The MOP of claim 1 , wherein the plurality of memory chips includes Double Data Rate fifth generation (DDR5) or sixth generation (DDR6) memory chips.
5 . The MOP of claim 1 , wherein the CAMM includes multiple arrays of signal coupling elements for coupling signals for multiple memory channels.
6 . The MOP of claim 1 , wherein the CAMM comprises a first CAMM, and the CMT connector comprises a first CMT connector, and wherein the first substrate further comprises one or more third arrays of CMT contact pads disposed on its topside and means for coupling signals for at least one of the CPU, SoC, and XPU to the one or more third arrays of CMT contact pads, further comprising:
a second CAMM comprising,
a third substrate including a one or more fourth arrays of compression mount technology (CMT) contact pads disposed on a first side, a plurality of third signal coupling arrays comprising a third arrays of signal coupling means disposed on the first side and wiring connecting CMT contact pads to signal coupling means in the plurality of third signal coupling arrays; and
multiple memory chips or packages, each comprising a fourth signal coupling array comprising a fourth array of signal coupling means, wherein the signal coupling means in the fourth signal coupling array for a given memory chip or package are coupled to signal coupling means in a respective third signal coupling array on the third substrate; and
a second CMT connector disposed between the third substate of the second CAMM and the first substrate, wherein the second CMT connector includes an array of spring-loaded contacts or pins in contact with CMT contact pads in the one or more third arrays of CMT contact pads and one or more fourth arrays of CMT contact pads.
7 . A platform, comprising:
a first substrate having one or more of a Central Processing Unit (CPU), System on a Chip (SoC), and other processing unit (XPU) mounted to a topside thereof and including one or more first arrays of compression mount technology (CMT) contacts pads disposed on the topside and means for coupling signals for at least one or the CPU, SoC, and XPU to the one or more first array of CMT contact pads;
a printed circuit board (PCB) to which the first substrate is coupled;
a Compression Attached Memory Module (CAMM) comprising,
a second substrate including a one or more second arrays of compression mount technology (CMT) contact pads disposed on a first side, a plurality of arrays of Ball Grid Array (BGA) pads disposed on the first side, and wiring connecting CMT contact pads to BGA pads in the arrays of BGA pads; and
multiple memory chips or packages, each comprising a BGA package coupled to a respective array of BGA pads on the second substate via a plurality of solder balls; and
a CMT connector disposed between the first substrate and the second substrate, wherein the CMT connector includes an array of spring-loaded contacts or pins in contact with CMT contact pads in the one or more first arrays and one or more second arrays of CMT contact pads.
8 . The platform of claim 7 , further comprising a structural means disposed between the CAMM and the PCB to facilitate structure integrity.
9 . The platform of claim 8 , wherein the structural means includes a thermal gasket and gap filler material.
10 . The platform of claim 8 , further comprising a thermal dissipation means thermally coupled to a topside of a CPU, SoC, or XPU mounted to the first substrate.
11 . The platform of claim 7 , wherein the CAMM comprises a first CAMM, and the CMT connector comprises a first CMT connector, and wherein the first substrate further comprises a third array of CMT contact pads disposed on its topside and means for coupling signals for at least one or the CPU, SoC, and XPU to the third array of CMT contact pads, further comprising:
a second CAMM comprising,
a third substrate including a one or more fourth arrays of compression mount technology (CMT) contact pads disposed on a first side, a plurality of arrays of Ball Grid Array (BGA) pads disposed on the first side, and wiring connecting CMT contact pads to BGA pads in the arrays of BGA pads; and
multiple memory chips or packages, each comprising a BGA package coupled to a respective array of BGA pads on the third substate via a plurality of solder balls; and
a second CMT connector disposed between the third substate of the second CAMM and the first substrate, wherein the second CMT connector includes an array of spring-loaded contacts or pins in contact with CMT contact pads in the one or more third arrays of CMT contact pads and one or more fourth arrays of CMT contact pads.
12 . The platform of claim 8 , further comprising a bolster plate disposed above the second substrate proximate to the one or more second arrays of CMT contact pads, and first and second fasteners, wherein the first and second fasteners are coupled one or the first substrate and the PCB and apply a downward force to the bolster plate to cause the CMT spring-loaded contacts or pins in the CMT connector to be compressed against CMT contact pads in the one or more first and one or more second arrays of CMT contact pads.
13 . The platform of claim 8 , wherein the plurality of memory chips or packages includes Low Power Double Data Rate (LPDDR), Double Data Rate fourth generation (DDR4), fifth generation (DDR5) or sixth generation (DDR6) memory chips or packages.