Self-aligned vertical solid state devices fabrication and integration methods
Various embodiments include methods of fabricating an array of self-aligned vertical solid state devices and integrating the devices to a system substrate. The method of fabricating a self-aligned vertical solid state device comprising: providing a semiconductor substrate, depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers comprises an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer that does not substantially etch the active layer.
1 . A method of manufacturing an optoelectronic panel, the method comprising:
fabricating an array of microdevices on a wafer substrate by forming a plurality of device layers on a top of the wafer substrate, each microdevice within the array of microdevices including positive sloped sidewalls;
prior to any bonding of the microdevices to another substrate and any removal of the microdevices from the wafer substrate, depositing a planarization layer on top of the plurality of device layers to isolate individual microdevices;
providing a system substrate with contact pads;
aligning the array of microdevices on the wafer substrate with the contact pads on the system substrate; and
bonding the array of microdevices to the system substrate,
wherein a width of the contact pads is at least two times larger than a width of the array of microdevices,
wherein each microdevice is formed from at least one device layer of the plurality of device layers on the wafer substrate and a generally planar ohmic contact on the at least one device layer, and
wherein the positive sloped sidewalls of each microdevice are formed from at least (i) a first dielectric layer having positive sloped sidewalls surrounding the ohmic contact and (ii) a passivation layer on the first dielectric layer having positive sloped sidewalls surrounding the ohmic contact.
2 . The method of claim 1 , wherein the plurality of device layers comprises a buffer layer, a polymer layer, conductive/metal layer(s), the passivation layer, and/or a dielectric layer.
3 . The method of claim 1 , wherein a second planarization or passivation layer is formed between the isolated individual microdevices.
4 . The method of claim 3 , wherein the second planarization layer comprises a polymer layer or an adhesive film layer.
5 . The method of claim 1 , wherein a second planarization layer is formed between the contact pads of the system substrate.
6 . The method of claim 1 , wherein the system substrate comprises driving circuitry and the contact pads are coupled to the driving circuitry.
7 . The method of claim 1 , further comprising removing the wafer substrate using a laser liftoff process.
8 . The method of claim 1 , wherein the system substrate comprises a TFT backplane.
9 . The method of claim 1 , wherein fabricating the array of microdevices on the wafer substrate comprises:
depositing the plurality of device layers on the wafer substrate, wherein the plurality of device layers comprises an active layer and a doped conductive layer;
depositing an ohmic contact layer on an upper surface of one device layer of the plurality of device layers;
forming a patterned metal conductive layer on the ohmic contact layer; and
selectively etching down the doped conductive layer.
10 . The method of claim 9 , further comprising etching a bottom layer of the plurality of device layers to expose bottom contacts.
11 . The method of claim 1 , wherein the positive sloped sidewalls of each microdevice are further formed from a conductive layer on the passivation layer having positive sloped sidewalls surrounding the ohmic contact.
12 . The method of claim 11 , wherein the positive sloped sidewalls of each microdevice are further formed from a second dielectric layer on the conductive layer having positive sloped sidewalls surrounding the ohmic contact.
13 . The method of claim 11 , wherein the positive sloped sidewalls of each microdevice are further formed from a reflective layer on the conductive layer having positive sloped sidewalls surrounding the ohmic contact.