Method of making a fan-out semiconductor assembly with an intermediate carrier
A semiconductor assembly comprising an intermediate carrier which is not an interposer and does not comprise electrical routing in or on the intermediate carrier, a plurality of components disposed over the intermediate carrier such that an active surface of the plurality of components is oriented away from the intermediate carrier, where the plurality of components have a thickness in a range of 2-500 micrometers (μm) and one or more components comprise conductive studs disposed over a front surface, an encapsulant contacting the intermediate carrier and the plurality of components, where the encapsulant contacts sides of the conductive studs, four side surfaces and the front surface of the plurality of components, and the encapsulant comprises a planar surface above the front surface of the plurality of components, and the planar surface comprises ends of the conductive studs and a planar surface of the encapsulant.
1 . A semiconductor assembly, comprising:
a solder mask layer having a plurality of solder mask openings;
a plurality of components each disposed face up within one of the plurality of solder mask openings, wherein the plurality of components have a thickness in a range of 2-500 micrometers (μm), each of the plurality of components comprising a conductive backside, and one or more components of the plurality of components comprise conductive studs disposed over a front surface of the plurality of components;
an encapsulant contacting the plurality of components and the solder mask layer, and extending into the plurality of solder mask openings between the solder mask layer and each of the plurality of components, wherein the encapsulant contacts sides of the conductive studs, four side surfaces and the front surface of the plurality of components; and
at least one planar surface above the front surface of the plurality of components, the at least one planar surface comprising a first planar surface comprising ends of the conductive studs and an encapsulant planar surface.
2 . The semiconductor assembly of claim 1 , wherein the plurality of components comprises one or more of: an active device, a passive device, an integrated circuit (IC), an IPD, a MEMS device, a sensor, a semiconductor chip, a transistor, a diode, a chiplet, an LED, a VCSEL, an RF device, a microwave device, a photonic device, and a bridge die, which comprise a footprint with edge lengths in a range of 0.15-25 millimeters (mm).
3 . The semiconductor assembly of claim 1 , wherein the thickness of the plurality of components is within a range of 2-125 μm.
4 . The semiconductor assembly of claim 1 , wherein the semiconductor assembly comprises at least a portion of one or more component pads.
5 . The semiconductor assembly of claim 1 , further comprising a fan-in or fan-out build-up interconnect structure contacting the planar surface and coupled to one or more of the plurality of components.
6 . The semiconductor assembly of claim 1 , wherein one or more components do not comprise conductive studs, and comprise contact pads disposed on a front surface of the plurality of components.
7 . The semiconductor assembly of claim 1 , wherein the plurality of components are each disposed face up within one of the plurality of solder mask openings such that an active layer of the plurality of components is oriented away from the solder mask layer.
8 . The semiconductor assembly of claim 1 , wherein the conductive backside of each of the plurality of components comprises a thermally conductive backside material comprising one or more layers of metal.
9 . A semiconductor assembly, comprising:
a solder mask layer having a plurality of solder mask openings;
a plurality of components each disposed within one of the plurality of solder mask openings, wherein the plurality of components have a thickness in a range of 2-500 micrometers (μm) and a conductive backside; and
an encapsulant contacting the plurality of components and the solder mask layer and extending into the solder mask openings between the solder mask layer and each of the plurality of components, wherein the encapsulant contacts four side surfaces and a front surface of the plurality of components and comprises at least one planar surface above the front surface of the plurality of components comprising an encapsulant planar surface.
10 . The semiconductor assembly of claim 9 , wherein one or more of the plurality of components comprise conductive studs disposed over the front surface, wherein the encapsulant contacts sides of the conductive studs.
11 . The semiconductor assembly of claim 10 , wherein one or more components comprise contact pads disposed on a front surface of the plurality of components and do not comprise conductive studs.
12 . The semiconductor assembly of claim 10 , wherein the planar surface comprises ends of the conductive studs and an encapsulant planar surface.
13 . The semiconductor assembly of claim 9 , wherein the plurality of components comprises one or more of: an active device, a passive device, an integrated circuit (IC), an IPD, a MEMS device, a sensor, a semiconductor chip, a transistor, a diode, a chiplet, an LED, a VCSEL, an RF device, a microwave device, a photonic device, and a bridge die, which comprise a footprint with edge lengths in a range of 0.15-25 millimeters (mm).
14 . The semiconductor assembly of claim 9 , further comprising a fan-in or fan-out build-up interconnect structure contacting the planar surface and over each of the plurality of components, that extends beyond an edge of each of the plurality of components.
15 . The semiconductor assembly of claim 9 , wherein the semiconductor assembly comprises at least a portion of one or more component pads.
16 . The semiconductor assembly of claim 9 , wherein the plurality of components are each disposed face up within one of the plurality of solder mask openings such that an active layer of the plurality of components is oriented away from the solder mask layer.
17 . The semiconductor assembly of claim 9 , further comprising a thermal frame disposed around a perimeter of each of the plurality of solder mask openings.
18 . A semiconductor assembly, comprising:
a solder mask layer having a plurality of solder mask openings;
a plurality of components, wherein each of the plurality of components is within one of the plurality of solder mask openings, wherein the plurality of components have a thickness in a range of 2-500 micrometers (μm), each of the plurality of components comprising a conductive backside, and one or more components of the plurality of components comprise conductive studs disposed over a front surface of the plurality of components;
an encapsulant contacting the plurality of components and the solder mask layer and extending into the solder mask openings between the solder mask layer and each of the plurality of components, wherein the encapsulant contacts sides of the conductive studs, four side surfaces and the front surface of the plurality of components;
at least one planar surface above the front surface of the plurality of components, the at least one planar surface comprising a first planar surface comprising ends of the conductive studs and an encapsulant planar surface.
19 . The semiconductor assembly of claim 18 , further comprising a fan-in or fan-out build-up interconnect structure contacting the planar surface that extends beyond an edge of each of the plurality of components.
20 . The semiconductor assembly of claim 18 , further comprising a component pad within each of the plurality of solder mask openings, wherein the conductive backside of each of the plurality of components is disposed on the component pad.