Redistribution structure with copper bumps on planar metal interconnects and methods of forming the same
First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.
1 . A method of forming a semiconductor structure, comprising:
forming first redistribution interconnect structures of an interposer on a top surface of a first adhesive layer over a first carrier wafer, wherein each of the first redistribution interconnect structures has a respective first planar surface located entirely within a first horizontal plane and a respective second planar surface located entirely within a second horizontal plane, the respective second planar surface having a same area as the respective first planar surface for each of the first redistribution interconnect structures;
forming redistribution dielectric layers and additional redistribution interconnect structures over the first redistribution interconnect structures, whereby at least one redistribution structure including a respective subset of the first redistribution interconnect structures, a respective portion of the redistribution dielectric layers, and a respective subset of the additional redistribution interconnect structures is formed;
attaching a respective set of one or more semiconductor dies to each of the at least one redistribution structure while the first adhesive layer and the first carrier wafer are attached to a backside of the at least one redistribution structure;
physically exposing the first planar surfaces of the first redistribution interconnect structures by removing the first carrier wafer and the first adhesive layer after the respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure; and
forming fan-out bump structures on the physically exposed first planar surfaces of the first redistribution interconnect structures.
2 . The method of claim 1 , wherein all of the physically exposed first planar surfaces of the first redistribution interconnect structures are located entirely within the first horizontal plane.
3 . The method of claim 1 , further comprising:
depositing a first continuous barrier metal layer and a first continuous copper seed layer over the top surface of the first adhesive layer;
forming a first patterned electroplating mask layer over the first continuous copper seed layer; electroplating copper on physically exposed surfaces of the first continuous copper seed layer within openings through the first patterned electroplating mask layer; and
removing the first patterned electroplating mask layer and portions of the first continuous copper seed layer and the first continuous barrier metal layer that are not covered by electroplated portions of copper.
4 . The method of claim 1 , wherein:
each of the first redistribution interconnect structures comprises a vertical stack of a respective first barrier metal layer and a first copper plate portion; and
planar surfaces of the first barrier metal layer are formed directly on the top surface of the first adhesive layer within the first horizontal plane.
5 . The method of claim 4 , wherein: the planar surfaces of the first redistribution interconnect structures are physically exposed upon removal of the first adhesive layer; and the fan-out bump structures are formed directly on the planar surfaces of the first redistribution interconnect structures.
6 . The method of claim 1 , further comprising forming on-interposer bump structures on topmost redistribution interconnect structures to the additional redistribution interconnect structures, wherein each set of the one or more semiconductor dies is attached to a respective subset of the on-interposer bump structures.
7 . The method of claim 1 , wherein:
the at least one redistribution structure comprises a two-dimensional array of redistribution structures; a two-dimensional array of sets one or more semiconductor dies is attached to the two-dimensional array of redistribution structures; and
the method comprises dicing the two-dimensional array of redistribution structures, whereby a plurality of fan-out semiconductor dies is formed.
8 . The method of claim 7 , further comprising forming a molding compound matrix around the two-dimensional array of semiconductor die sets, wherein each of the plurality of fan-out semiconductor dies comprises a molding compound die frame that includes a respective diced portion of the molding compound matrix.
9 . The method of claim 1 , further comprising:
forming a substrate-side dielectric layer directly on the first redistribution interconnect structures; and
forming via openings through the substrate-side dielectric layer, wherein the fan-out bump structures fill the via openings.
10 . The method of claim 9 , further comprising:
depositing a continuous barrier metal layer and a continuous copper seed layer over the first planar surfaces of the first redistribution interconnect structures;
forming a patterned electroplating mask layer over the continuous copper seed layer;
electroplating copper on physically exposed surfaces of the continuous copper seed layer within openings through the patterned electroplating mask layer; and
removing the patterned electroplating mask layer and portions of the continuous copper seed layer and the continuous barrier metal layer that are not covered by electroplated portions of copper.
11 . The method of claim 1 , wherein each of the fan-out bump structures comprises a respective copper portion that formed directly on the first planar surface of a respective one of the first redistribution interconnect structures.
12 . The method of claim 11 , further comprising:
depositing a continuous copper seed layer directly on the first planar surfaces of the first redistribution interconnect structures;
forming a patterned electroplating mask layer over the continuous copper seed layer;
electroplating copper on physically exposed surfaces of the continuous copper seed layer within openings through the patterned electroplating mask layer; and
removing the patterned electroplating mask layer and portions of the continuous copper seed layer that are not covered by electroplated portions of copper.
13 . A method of forming a semiconductor structure, comprising:
forming first redistribution interconnect structures of an interposer on a top surface of a first adhesive layer over a first carrier wafer, wherein each of the first redistribution interconnect structures has a respective first planar surface located entirely within a first horizontal plane;
forming redistribution dielectric layers and additional redistribution interconnect structures over the first redistribution interconnect structures, whereby at least one redistribution structure including a respective subset of the first redistribution interconnect structures, a respective portion of the redistribution dielectric layers, and a respective subset of the additional redistribution interconnect structures is formed;
attaching a respective set of one or more semiconductor dies to each of the at least one redistribution structure while the first adhesive layer and the first carrier wafer are attached to a backside of the at least one redistribution structure;
physically exposing the first planar surfaces of the first redistribution interconnect structures by removing the first carrier wafer and the first adhesive layer after the respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure; and
forming fan-out bump structures on the physically exposed first planar surfaces of the first redistribution interconnect structures.
14 . The method of claim 13 , wherein all of the physically exposed first planar surfaces of the first redistribution interconnect structures are located entirely within the first horizontal plane.
15 . The method of claim 13 , further comprising:
depositing a first continuous barrier metal layer and a first continuous copper seed layer over the top surface of the first adhesive layer;
forming a first patterned electroplating mask layer over the first continuous copper seed layer; electroplating copper on physically exposed surfaces of the first continuous copper seed layer within openings through the first patterned electroplating mask layer; and
removing the first patterned electroplating mask layer and portions of the first continuous copper seed layer and the first continuous barrier metal layer that are not covered by electroplated portions of copper.
16 . The method of claim 13 , wherein:
each of the first redistribution interconnect structures comprises a vertical stack of a respective first barrier metal layer and a first copper plate portion; and
planar surfaces of the first barrier metal layer are formed directly on the top surface of the first adhesive layer within the first horizontal plane.
17 . A method of forming a semiconductor structure, comprising:
forming first redistribution interconnect structures of an interposer on a top surface of a first adhesive layer over a first carrier wafer, wherein each of the first redistribution interconnect structures has a respective first planar surface located entirely within a first horizontal plane;
forming redistribution dielectric layers and additional redistribution interconnect structures over the first redistribution interconnect structures, whereby at least one redistribution structure including a respective subset of the first redistribution interconnect structures, a respective portion of the redistribution dielectric layers, and a respective subset of the additional redistribution interconnect structures is formed;
attaching a respective set of one or more semiconductor dies to each of the at least one redistribution structure while the first adhesive layer and the first carrier wafer are attached to a backside of the at least one redistribution structure;
removing the first carrier wafer and the first adhesive layer after the respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure; and
forming fan-out bump structures on the physically exposed first planar surfaces of the first redistribution interconnect structures.
18 . The method of claim 13 , further comprising forming on-interposer bump structures on topmost redistribution interconnect structures to the additional redistribution interconnect structures, wherein each set of the one or more semiconductor dies is attached to a respective subset of the on-interposer bump structures.
19 . The method of claim 13 , wherein:
the at least one redistribution structure comprises a two-dimensional array of redistribution structures; a two-dimensional array of sets one or more semiconductor dies is attached to the two-dimensional array of redistribution structures; and
the method comprises dicing the two-dimensional array of redistribution structures, whereby a plurality of fan-out semiconductor dies is formed.
20 . The method of claim 13 , further comprising:
forming a substrate-side dielectric layer directly on the first redistribution interconnect structures; and
forming via openings through the substrate-side dielectric layer, wherein the fan-out bump structures fill the via openings.