IP Library Granted Patent US 12704476
Granted Patent B2
US 12704476 · App. 18/333,485 · Granted Aug 11, 2026

Semiconductor structure, integrated circuit and manufacturing method thereof

Inventors: I-Che Lee (Hsinchu, TW); Huai-Ying Huang (New Taipei City, TW); Yen-Chieh Huang (Hsinchu, TW); Kai-Wen Cheng (Taichung City, TW); Yu-Ming Lin (Hsinchu City, TW); Chung-Te Lin (Tainan City, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
G01N27/4141G01N27/4148G01N33/005H10W20/435
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Quick Facts
Patent No.
US 12704476
App. No.
18/333,485
Granted
Aug 11, 2026
Kind
B2
Abstract

A semiconductor structure is disclosed. The semiconductor structure includes a semiconductor substrate, a hydrogen sensing stacked layer disposed over the semiconductor substrate, and a protection layer disposed on the hydrogen sensing stacked layer. The hydrogen sensing stacked layer comprises a hydrogen-free oxide layer and a metal oxide layer disposed on the hydrogen-free oxide layer.

Claims (36)

1 . A semiconductor structure, comprising:

a semiconductor substrate;

a hydrogen sensing stacked layer disposed over the semiconductor substrate, the hydrogen sensing stacked layer comprising a hydrogen-free oxide layer and a metal oxide layer disposed on the hydrogen-free oxide layer; and

a dielectric protection layer disposed on the hydrogen sensing stacked layer.

2 . The semiconductor structure of claim 1 , wherein the metal oxide layer is between the dielectric protection layer and the hydrogen-free oxide layer, and the hydrogen-free oxide layer is between the semiconductor substrate and the metal oxide layer.

3 . The semiconductor structure of claim 1 , wherein the dielectric protection layer comprises a single layer, and the single layer comprises an aluminum oxide (AlO x ) layer.

4 . The semiconductor structure of claim 1 , wherein the dielectric protection layer comprises a stacked layer, and the stacked layer comprises a silicon oxide layer and an aluminum oxide (AlO x ) layer disposed on the silicon oxide layer.

5 . The semiconductor structure of claim 1 , wherein a hydrogen sensing interface is located between the hydrogen-free oxide layer and the metal oxide layer, and a distance between the hydrogen sensing interface and a surface of the dielectric protection layer ranges from −200 Å to −2 μm.

6 . The semiconductor structure of claim 1 , wherein the hydrogen-free oxide layer comprises silicon nitride, Al 2 O 3 , HfO, ZrO, or TiO.

7 . The semiconductor structure of claim 1 , wherein the metal oxide layer comprises InGaZnO, InO, GaO, ZnO, AlO, SnO, or CuO.

8 . The semiconductor structure of claim 1 , wherein the hydrogen sensing stacked layer serves as a channel layer of a transistor, the transistor further comprises a gate electrode, a source electrode, and a drain electrode, and the gate electrode is in contact with the hydrogen-free oxide layer.

9 . An integrated circuit (IC), comprising:

a semiconductor substrate comprising semiconductor devices;

an interconnect structure disposed on the semiconductor substrate; and

a hydrogen sensor embedded in the interconnect structure, wherein the hydrogen sensor comprises a transistor having a gate electrode, a source electrode, and a drain electrode and a hydrogen sensing stacked layer, the hydrogen sensing stacked layer serves as a channel layer of the transistor, the hydrogen sensing stacked layer comprises a hydrogen-free oxide layer and a metal oxide layer disposed on the hydrogen-free oxide layer, and the gate electrode is in contact with the hydrogen-free oxide layer.

10 . The semiconductor structure of claim 9 , wherein a hydrogen sensing interface is located between the hydrogen-free oxide layer and the metal oxide layer, and a distance between the hydrogen sensing interface and a surface of the metal oxide layer ranges from 200 Å to 2 μm.

11 . The semiconductor structure of claim 9 , wherein the gate electrode is between the hydrogen sensing stacked layer and the interconnect structure.

12 . The semiconductor structure of claim 9 , wherein the source electrode and the drain electrode are disposed on and electrically connected to the metal oxide layer.

13 . The semiconductor structure of claim 9 , further comprising:

a protection layer disposed on the hydrogen sensing stacked layer.

14 . The semiconductor structure of claim 13 , wherein the protection layer comprises a single layer, and the single layer comprises an aluminum oxide (AlO x ) layer.

15 . The semiconductor structure of claim 13 , wherein the protection layer comprises a stacked layer, and the stacked layer comprises a silicon oxide layer and an aluminum oxide (AlO x ) layer disposed on the silicon oxide layer.

16 . The semiconductor structure of claim 13 , wherein a hydrogen sensing interface is located between the hydrogen-free oxide layer and the metal oxide layer, and a distance between the hydrogen sensing interface and a surface of the protection layer ranges from 200 Å to 2 μm.

17 . A method of manufacturing an integrated circuit (IC) device, comprising:

providing a semiconductor substrate comprising semiconductor devices; and

forming an interconnect structure comprising an embedded hydrogen sensor, wherein the interconnect structure is disposed on the semiconductor substrate, the interconnect structure is electrically connected to the semiconductor devices, and a method for forming the interconnect structure comprises:

forming first stacked dielectric layers and interconnect wirings embedded in the first stacked dielectric layer;

forming the embedded hydrogen sensor on the first stacked dielectric layers; and

forming second stacked dielectric layers covering the first stacked dielectric layers and the embedded hydrogen sensor.

18 . The method of claim 17 , wherein the method for forming the interconnect structure further comprises:

forming a protection layer on the hydrogen sensing stacked layer.

19 . The method of claim 18 , wherein

the protection layer comprises an aluminum oxide (AlO x ) layer.

20 . The method of claim 17 , wherein the method for forming the interconnect structure further comprises:

forming a gate electrode in contact with the hydrogen-free oxide layer; and

forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are disposed on and electrically connected to the metal oxide layer.