IP Library Granted Patent US 12704524
Granted Patent B2
US 12704524 · App. 18/312,604 · Granted Aug 11, 2026

Method and apparatus for testing a semiconductor device

Inventors: ZunBae Moon (Gyeonggi-do, KR); WonJung Kim (Incheon, KR); KyouYong Han (Incheon, KR)
G01R1/0433G01R1/06722
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12704524
App. No.
18/312,604
Filed
May 5, 2023
Granted
Aug 11, 2026
Kind
B2
Art Unit
2858
USPC
324/754.03
Abstract

A method and an apparatus for testing a semiconductor device are provided. The apparatus includes: one or more ground contacts configured for coupling to one or more ground terminals of the semiconductor device respectively; and a detection module having one or more inputs coupled to the one or more ground contacts respectively, and configured to detect electrical conditions at the one or more ground contacts; wherein, when the semiconductor device is mounted on the test apparatus, a first signal is generated at an output of the detection module if all of the one or more ground contacts are coupled to the one or more ground terminals of the semiconductor device, and a second signal different from the first signal is generated at the output of the detection module if at least one of the one or more ground contacts is not coupled to the one or more ground terminals.

Claims (30)

1 . A test apparatus for testing a semiconductor device, wherein the semiconductor device comprises a plurality of ground terminals, and the test apparatus comprises:

a plurality of ground contacts configured for coupling to the plurality of ground terminals of the semiconductor device respectively; and

a detection module having a plurality of inputs coupled to the plurality of ground contacts respectively, and configured to detect electrical conditions at the plurality of ground contacts;

wherein, when the semiconductor device is mounted on the test apparatus for testing, a first signal is generated at an output of the detection module if all of the plurality of ground contacts are coupled to the plurality of ground terminals of the semiconductor device, and a second signal different from the first signal is generated at the output of the detection module if at least one of the plurality of ground contacts is not coupled to the plurality of ground terminals of the semiconductor device; and

wherein the semiconductor device comprises a power terminal, the test apparatus comprises a power contact configured for coupling to the power terminal of the semiconductor device, and the test apparatus further comprises:

a control module coupled between the output of the detection module and the power contact of the test apparatus, wherein the control module is configured to apply an external power supply on the power contact of the test apparatus when receiving the first signal from the output of the detection module.

2 . The test apparatus of claim 1 , wherein the detection module comprises a NOR gate, the first signal is a logic high voltage and the second signal is logical low voltage.

3 . The test apparatus of claim 1 , wherein the control module comprises a low-dropout regulator or a load switch.

4 . The test apparatus of claim 1 , further comprising:

an indicator coupled to the output of the detection module, wherein the indicator is configured to provide a notification to indicate that the semiconductor device is correctly mounted on the test apparatus, when receiving the first signal from the output of the detection module.

5 . The test apparatus of claim 4 , wherein the indicator comprises a light indicator or a sound indicator.

6 . The test apparatus of claim 1 , wherein the test apparatus comprises a test socket, and the plurality of ground contacts are Pogo pins.

7 . The test apparatus of claim 1 , wherein the detection module is formed on a flexible printed circuit board.

8 . A method for testing a semiconductor device, comprising:

providing a semiconductor device comprising a power terminal and a plurality of ground terminals;

providing a test apparatus, wherein the test apparatus comprises:

a power contact configured for coupling to the power terminal of the semiconductor device;

a plurality of ground contacts configured for coupling to the plurality of ground terminals of the semiconductor device respectively;

a detection module having a plurality of inputs coupled to the plurality of ground contacts respectively, and configured to detect electrical conditions at the plurality of ground contacts; and

a control module coupled between an output of the detection module and the power contact of the test apparatus;

mounting the semiconductor device on the test apparatus; and

generating an indication signal at the output of the detection module, wherein the indication signal has a first logic level if all of the plurality of ground contacts are coupled to the plurality of ground terminals of the semiconductor device, and the indication signal has a second logic level different from the first logic level if at least one of the plurality of ground contacts is not coupled to the plurality of ground terminals of the semiconductor device; and

applying, by the control module, an external power supply on the power contact of the test apparatus when receiving the indication signal having the first logic level from the output of the detection module.

9 . The method of claim 8 , wherein the detection module comprises a NOR gate, the indication signal has a logic high voltage if all of the plurality of ground contacts are coupled to the plurality of ground terminals of the semiconductor device, and the indication signal has a logic low voltage if at least one of the plurality of ground contacts is not coupled to the plurality of ground terminals of the semiconductor device.

10 . The method of claim 8 , wherein the control module comprises a low-dropout regulator or a load switch.

11 . The method of claim 8 , wherein the test apparatus further comprises an indicator coupled to the output of the detection module, and the method further comprises:

providing, by the indicator, a notification to indicate that the semiconductor device is correctly mounted on the test apparatus, when the indicator receives the indication signal having the first logic level from the output of the detection module.

12 . The method of claim 11 , wherein the indicator comprises a light indicator or a sound indicator.

13 . The method of claim 8 , wherein the test apparatus comprises a test socket, and the plurality of ground contacts are Pogo pins.

14 . The method of claim 8 , wherein the detection module is formed on a flexible printed circuit board.