I/O hardware power management
The disclosed device includes an input/output (I/O) system clock configured to operate at one of a plurality of clock states and a control circuit configured to dynamically adjust a clock state of the I/O system clock. The control circuit can update an activity level of a current clock state based at least on I/O traffic activity and, in response to the activity level going beyond an activity range for the current clock state, transition the I/O system clock to a neighboring clock state. Various other methods, systems, and computer-readable media are also disclosed.
1 . A device comprising:
a control circuit configured to dynamically adjust a clock state of an input/output (I/O) system clock by:
updating an activity level value of a first clock state of the I/O system clock based at least on I/O traffic activity, wherein the control circuit is configured to update the activity level value by:
incrementing the activity level value based on the I/O traffic activity from an activity monitor, while decrementing the activity level value based on a decrement rate over time; and
in response to the activity level value going beyond an activity range for the first clock state, transitioning the I/O system clock to a second clock state.
2 . The device of claim 1 , wherein the decrement rate corresponds to a predicted rate of outgoing I/O traffic over time.
3 . The device of claim 1 , wherein the decrement rate corresponds to an observed rate of outgoing I/O traffic over time.
4 . The device of claim 1 , wherein the control circuit is configured to transition the I/O system clock by transitioning, in response to the activity level value exceeding an upper threshold of the activity range, the I/O system clock to an available higher performance clock state.
5 . The device of claim 1 , wherein the control circuit is configured to transition the I/O system clock by transitioning, in response to the activity level value falling below a lower threshold of the activity range, the I/O system clock to an available lower performance clock state.
6 . The device of claim 1 , wherein the control circuit is configured to transition the I/O system clock by initializing an activity level value for the transitioned clock state.
7 . The device of claim 1 , wherein each of a plurality of clock states, which includes the first clock state and the second clock state, is associated with a programmable initial activity level value, a programmable decrement rate, and a programmable activity range comprising an upper threshold and a lower threshold.
8 . The device of claim 1 , wherein each of a plurality of clock states, which includes the first clock state and the second clock state, corresponds to a clock frequency and the device further comprises a frequency selection circuit configured to select a desired clock frequency.
9 . The device of claim 8 , wherein the frequency selection circuit corresponds to a multiplexer.
10 . A system comprising:
an input/output (I/O) system comprising:
an I/O system clock configured to operate at one of a plurality of clock states, each of the plurality of clock states corresponding to a clock frequency;
a frequency selection circuit coupled to the I/O system clock and configured to select between the plurality of clock states; and
an activity monitor configured to observe I/O traffic activity; and
a control circuit configured to dynamically adjust a clock state of the I/O system clock by:
updating an activity level of a first clock state based at least on the I/O traffic activity, wherein the control circuit is configured to update the activity level by:
incrementing the activity level based on the I/O traffic activity from the activity monitor, while decrementing the activity level based on a decrement rate over time; and
in response to the activity level going beyond an activity range for the first clock state, transitioning the I/O system clock to a second clock state.
11 . The system of claim 10 , wherein the decrement rate corresponds to a predicted rate of outgoing I/O traffic over time.
12 . The system of claim 10 , wherein the decrement rate corresponds to an observed rate of outgoing I/O traffic over time.
13 . The system of claim 10 , wherein the control circuit is configured to transition the I/O system clock by transitioning, in response to the activity level exceeding an upper threshold of the activity range, the I/O system clock to an available higher performance clock state.
14 . The system of claim 10 , wherein the control circuit is configured to transition the I/O system clock by transitioning, in response to the activity level falling below a lower threshold of the activity range, the I/O system clock to an available lower performance clock state.
15 . The system of claim 10 , wherein each of the plurality of clock states is associated with a programmable initial activity level value, a programmable decrement rate, and a programmable activity range comprising an upper threshold and a lower threshold, and the control circuit is configured to transition the I/O system clock by initializing an activity level value for the transitioned clock state based on the programmable initial activity level value.
16 . The system of claim 10 , wherein the frequency selection circuit corresponds to a multiplexer.
17 . A method comprising:
incrementing an activity level of a first clock state of an I/O system clock based on I/O traffic activity from an activity monitor while decrementing the activity level based on a decrement rate over time; and
in response to the activity level going beyond an activity range for the first clock state, transitioning the I/O system clock to a second clock state.
18 . The method of claim 17 , wherein transitioning the I/O system clock further comprises:
transitioning, in response to the activity level exceeding an upper threshold of the activity range, the I/O system clock to an available higher performance clock state; and
transitioning, in response to the activity level falling below a lower threshold of the activity range, the I/O system clock to an available lower performance clock state.