Power grid allocation in extended reality (XR) devices
An apparatus includes multiple core devices, each core device configured to operate at multiple voltage levels. The apparatus also includes a power management integrated circuit (PMIC) comprising multiple power supplies, each power supply corresponding to one of the voltage levels. A first of the power supplies corresponds to a first voltage level selectively coupled to a first of the core devices configured to operate at the first voltage level. A second power supply of the power supplies corresponds to a second voltage level selectively coupled to the first of the core devices configured to operate at the second voltage level.
1 . An apparatus, comprising:
a plurality of core devices, each core device configured to operate at a plurality of voltage levels;
a power management integrated circuit (PMIC) comprising a plurality of power supplies, each power supply corresponding to one of the plurality of voltage levels, a first power supply of the plurality of power supplies corresponding to a first voltage level selectively coupled to a first core device of the plurality of core devices configured to operate at the first voltage level, a second power supply of the plurality of power supplies corresponding to a second voltage level selectively coupled to the first core device of the plurality of core devices configured to operate at the second voltage level; and
an artificial intelligence (AI) core coupled to a switch and to the PMIC, the switch selectively coupling the first core device to the first power supply and the second power supply, the AI core configured to control the switch and the PMIC based on receiving a current specification for the first core device, a voltage specification for the first core device, output voltages of the first power supply and the second power supply, and current ratings of the first power supply and the second power supply.
2 . The apparatus of claim 1 , further comprising a plurality of groups of package interconnects coupled to each core device, each group of package interconnects coupled to one of the plurality of power supplies.
3 . The apparatus of claim 1 , further comprising a switch selectively coupling the first core device to the first power supply and the second power supply, the switch located on the PMIC.
4 . The apparatus of claim 1 , further comprising a switch selectively coupling the first core device to the first power supply and the second power supply, the switch located outside of the PMIC.
5 . The apparatus of claim 1 , further comprising a switch selectively coupling the first core device to the first power supply and the second power supply, the switch located on a die comprising the plurality of core devices.
6 . The apparatus of claim 1 , further comprising a switch selectively coupling the first core device to the first power supply and the second power supply, the switch located on a printed circuit board (PCB) coupled to the PMIC and to a die comprising the plurality of core devices.
7 . The apparatus of claim 1 , further comprising means for selectively coupling the first core device to the first power supply and the second power supply, the selectively coupling means located on the PMIC.
8 . The apparatus of claim 1 , further comprising means for selectively coupling the first core device to the first power supply and the second power supply, the selectively coupling means located outside of the PMIC.
9 . The apparatus of claim 1 , further comprising means for selectively coupling the first core device to the first power supply and the second power supply, the selectively coupling means located on a die comprising the plurality of core devices.
10 . The apparatus of claim 1 , further comprising means for selectively coupling the first core device to the first power supply and the second power supply, the means located on a printed circuit board (PCB) coupled to the PMIC and to a die comprising the plurality of core devices.