IP Library › Granted Patent US 12704959

Granted Patent B2

US 12704959 · App. 19/061,742 · Granted Aug 11, 2026

Memory controller, operating method thereof, memory system, and storage medium

Inventor: Zhiwei Zhuang (Wuhan, CN)

Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

G06F3/0608 G06F3/0659 G06F3/0679

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Quick Facts

Patent No.: US 12704959
App. No.: 19/061,742
Granted: Aug 11, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

According to one aspect, the present disclosure provides a memory controller. The memory controller includes a first memory, an address manager, and a processor; the processor is configured to: write data of an N-th data packet in the first memory; the address manager is configured to: generate a first read address sequence according to a first write address sequence in which the data of the N-th data packet is written; the processor is configured to: update the first read address sequence into a first sequence table, read the data of the N-th data packet, and write data of an (N+1)-th data packet in the first memory; the address manager is configured to: generate a second read address sequence; and the processor is configured to: update the second read address sequence; and read the data of the (N+1)-th data packet according to the second read address sequence.

Claims (79)

1 . A memory controller, comprising:

a first memory;

an address manager; and

a processor, wherein

the processor is configured to: write data of an N-th data packet in the first memory, wherein N is a positive integer;

the address manager is configured to: generate a first read address sequence according to a first write address sequence in which the data of the N-th data packet is written in the first memory;

the processor is configured to: update the first read address sequence into a first sequence table, read the data of the N-th data packet written in the first memory according to the first read address sequence in the first sequence table, and write data of an (N+1)-th data packet in the first memory according to a second write address sequence in a process of reading the data of the N-th data packet;

the address manager is further configured to: generate a second read address sequence according to the second write address sequence; and

the processor is further configured to: update the second read address sequence into a second sequence table, and read the data of the (N+1)-th data packet written in the first memory according to the second read address sequence in the second sequence table.

2 . The memory controller of claim 1 , wherein an address ordering of the first write address sequence is different from an address ordering of the first read address sequence, or an address ordering of the second write address sequence is different from an address ordering of the second read address sequence.

3 . The memory controller of claim 1 , wherein the processor is configured to:

update a plurality of addresses in the first memory and state values corresponding to the plurality of addresses into an address state table in real time, wherein a state value of a corresponding address in the address state table being a first value represents that the address is in an idle state, and a state value of a corresponding address in the address state table being a second value represents that the address is in a non-idle state;

write the data of the N-th data packet to an idle address in the first memory for which a state value is the first value according to the address state table; and

write the data of the (N+1)-th data packet to an idle address in the first memory for which a state value is the first value according to the address state table.

4 . The memory controller of claim 3 , wherein

the address manager comprises a write address manager and a read address manager;

the write address manager is configured to: generate the first write address sequence according to the address state table and generate the second write address sequence according to the address state table; and

the read address manager is configured to: generate the first read address sequence according to the first write address sequence and generate the second read address sequence according to the second write address sequence.

5 . The memory controller of claim 1 , wherein

N is equal to 1;

before the data of the N-th data packet is written in the first memory, the first sequence table and the second sequence table are both in an idle state;

while the data of the N-th data packet is being written in the first memory, the first sequence table is in an updated state, and the second sequence table is in the idle state; and

after the data of the N-th data packet is written in the first memory, the first sequence table is in an output state, and the second sequence table is in the updated state.

6 . The memory controller of claim 1 , wherein

the N-th data packet comprises X M-bit data;

the (N+1)-th data packet comprises Y M-bit data;

a depth of the first memory is P; and

a bit width of the first memory is M, wherein X, Y, M, and N are all positive integers, and P is greater than a larger one of X and Y.

7 . The memory controller of claim 6 , wherein a difference between P and the larger one of X and Y is 1.

8 . The memory controller of claim 7 , wherein

X is greater than Y;

the processor is further configured to: in a process of reading the data of the N-th data packet, start writing data of an (N+2)-th data packet in the first memory according to a third write address sequence;

the address manager is further configured to: generate a third read address sequence according to the third write address sequence; and

the processor is further configured to: update the third read address sequence into a third sequence table, and read the data of the (N+2)-th data packet written in the first memory according to the third read address sequence in the third sequence table.

9 . The memory controller of claim 8 , wherein

the memory controller further comprises: a second memory; and

the processor is configured to: store the first sequence table, the second sequence table, and the third sequence table into the second memory.

10 . The memory controller of claim 6 , wherein P is less than twice the larger one of X and Y.

11 . The memory controller of claim 6 , wherein P is equal to the larger one of X and Y.

12 . The memory controller of claim 11 , wherein the processor is configured to:

at a first point-in-time after writing the data of the N-th data packet in the first memory, start reading a first data of the N-th data packet written in the first memory according to the first read address sequence in the first sequence table; and

at a second point-in-time after writing the data of the N-th data packet into the first memory, start writing the first data of the (N+1)-th data packet in the first memory according to the second write address sequence,

wherein a time interval between the first point-in-time and the second point-in-time is a period used by the processor to read one data of the N-th data packet.

13 . The memory controller of claim 1 , wherein the first memory comprises a static random access memory or a register.

14 . A method of operating a memory controller, comprising:

writing data of an N-th data packet in a first memory of the memory controller, wherein N is a positive integer;

generating a first read address sequence according to a first write address sequence in which the data of the N-th data packet is written in the first memory;

updating the first read address sequence into a first sequence table and reading the data of the N-th data packet written in the first memory according to the first read address sequence in the first sequence table, and writing data of an (N+1)-th data packet in the first memory according to a second write address sequence in a process of reading the data of the N-th data packet;

generating a second read address sequence according to the second write address sequence; and

updating the second read address sequence into a second sequence table, and reading the data of the (N+1)-th data packet written in the first memory according to the second read address sequence in the second sequence table.

15 . The method of claim 14 , wherein an address ordering of the first write address sequence is different from an address ordering of the first read address sequence, or an address ordering of the second write address sequence is different from an address ordering of the second read address sequence.

16 . The method of claim 14 , further comprising:

updating a plurality of addresses in the first memory and state values corresponding to the plurality of addresses into an address state table in real time, wherein a state value of a corresponding address in the address state table being a first value represents that the address is in an idle state, and a state value of a corresponding address in the address state table being a second value represents that the address is in a non-idle state;

writing the data of the N-th data packet to an idle address in the first memory for which a state value is the first value according to the address state table; and

writing the data of the (N+1)-th data packet to an idle address in the first memory for which a state value is the first value according to the address state table.

17 . The method of claim 16 , further comprising:

generating, by a write address manager of the memory controller, the first write address sequence according to the address state table and generating, by the write address manager of the memory controller, the second write address sequence according to the address state table; and

generating, by a read address manager of the memory controller, a first read address sequence according to the first write address sequence and generating, by the read address manager of the memory controller, the second read address sequence according to the second write address sequence.

18 . The method of claim 14 , wherein