Flash translation layer write path architecture for increased throughput

1 . A processing device comprising:

flash translation layer logic to be coupled to a memory device, wherein the flash translation layer logic comprises:

cursor logic to generate a criteria set associated with generating a backend command to be sent the memory device; and

a first streamer logic component, of multiple streamer logic components, coupled between the cursor logic and a backend that interfaces with the memory device, wherein the first streamer logic component is to access and employ the criteria set to perform operations comprising:

aggregating a plurality of translation units (TUs) received in one or more write messages, wherein the criteria set enables accessing the plurality of TUs within a first format, of the one or more write messages, that depends on a first data path associated with the one or more write messages, wherein the first data path is different than a second data path associated with a second streamer logic component of the multiple streamer logic components; and

formatting the aggregated plurality of TUs into the backend command having a second format for transmittal to the memory device via the backend, wherein the backend command is to direct the memory device in writing TU data, associated with the plurality of TUs, to a memory array of the memory device.

2 . The processing device of claim 1 , wherein the cursor logic is one of dedicated hardware or a processing core and is further to at least one of:

open and close a block stripe across a plurality of planes of the memory device;

allocate and track RAIN contexts of the memory device;

interact with a write sequencer to layout how write operations are to be ordered;

interact with a physical-to-logical (P2L) write unit to open and close P2L buffers; or

handle RAIN parity writes.

3 . The processing device of claim 1 , wherein the cursor logic is further to:

store the criteria set in a memory; and

provide, to the first streamer logic component, a pointer to the memory where the criteria set is stored.

4 . The processing device of claim 1 , wherein the criteria set comprises:

a location in the memory array where a write operation should be performed in response to the backend command; and

how the TU data is to be organized for being written to the location.

5 . The processing device of claim 1 , wherein the criteria set comprises information associated with at least two of:

a size of a page group comprising the aggregated plurality of TUs;

a number of valid buffers for the page group;

physical-to-logical (P2L) translation-specific information;

a first bitmask for bad planes of the memory device;

a second bitmask for parity planes of the memory device;

RAIN-related information; and

a flash logical address of the backend command.

6 . The processing device of claim 1 , wherein the first data path is one of a host data path, a folding write data path, a flash data manager (FDM) data path, or a post-persist physical-to-logical drop recovery data path.

7 . The processing device of claim 1 , wherein the operations further comprise:

interacting with a write message queue to retrieve TU data buffer addresses and TU address information in order to aggregate the plurality of TUs;

updating entries in a physical-to-logical (P2L) buffer associated with the TU address information; and

transmit the backend command to the memory device.

8 . The processing device of claim 1 , wherein the operations further comprise at least one of:

enabling reuse of entries within a backend command buffer for subsequent writes received from a host system; and

enabling reuse of a pool of pre-allocated backend commands in generating the backend command.

9 . The processing device of claim 1 , wherein the cursor logic is further to save a cursor state, associated with a first location in the memory array, to a data structure which is to be flushed to the memory array in response to a power down operation, wherein the cursor state is pushed to a second location within the memory array as a result of saving the cursor state.

10 . The processing device of claim 9 , wherein the cursor logic is further to:

in response to the power down operation, at least one of:

output one or more pointers to a source memory that are to be saved for physical-to-logical (P2L) buffers that exist; or

output one or more pointers to the source memory that are to be saved for RAIN buffers; and

in response to a power up operation, at least one of:

output one or more pointers to the source memory that are to be populated with saved P2L buffers; or

output one or more pointers to the source memory that are to be populated with saved RAIN buffers.

11 . The processing device of claim 9 , further comprising the second streamer logic component coupled to the cursor logic, the second streamer logic component to perform additional operations comprising causing, in response to powering up the processing device, a plurality of dummy writes to be performed so that the cursor logic is prompted to look for the cursor state at the second location upon restoring the cursor state as part of a power up operation.

12 . A system comprising:

a memory device comprising a memory array located across a plurality of planes; and

a processing device coupled to the memory device, the processing device comprising flash translation layer logic, which comprises:

first cursor logic to allocate storing data to a first block stripe across the plurality of planes and generate a first criteria set associated with generating a first backend command to be sent the memory device;

second cursor logic to allocate storing data to a second block stripe across the plurality of planes and generate a second criteria set associated with generating a second backend command to be sent the memory device; and

streamer logic coupled between the first and second cursor logic and a backend that interfaces with the memory device, wherein the streamer logic is to:

identify a first namespace identifier associated with first write messages to aggregate a first plurality of translation units (TUs) received in the first write messages;

identify a second namespace identifier associated with second write messages to aggregate a second plurality of TUs received in the second write messages; and

switch between accessing and employing one of the first criteria set or the second criteria set to one of generate the first backend command using the aggregated first plurality of TUs or the second backend command using the aggregated second plurality of TUs, respectively, based on identifying the first write messages to be processed as being associated with the first namespace identifier and the second write messages to be processed as being associated with the second namespace identifier.

13 . The system of claim 12 , wherein the streamer logic is to perform operations comprising:

determining the first write messages comprise the first namespace identifier associated with the first block stripe;

accessing the first criteria set at a first location in memory;

aggregating the first plurality of TUs received in the first write messages, wherein the first criteria set enables accessing the first plurality of TUs within a first format, of the first write messages, that depends on a data path associated with the first write messages; and

formatting the aggregated first plurality of TUs into the first backend command having a second format for transmittal to the memory device via the backend, wherein the first backend command is to direct the memory device in writing TU data, associated with the first plurality of TUs, to the first block stripe.

14 . The system of claim 13 , wherein the first criteria set comprises:

a location in the first block stripe where a write command should be performed in response to the first backend command; and

how the TU data is to be organized for being written to the location.

15 . The system of claim 13 , wherein the first criteria set comprises information associated with at least two of:

a size of a page group comprising the aggregated plurality of TUs;

a number of valid buffers for the page group;

physical-to-logical (P2L) translation-specific information;

a first bitmask for bad planes of the memory device;

a second bitmask for parity planes of the memory device;

RAIN-related information; and

a flash logical address of the backend command.

16 . The system of claim 13 , wherein the data path is one of a host data path, a folding write data path, a flash data manager (FDM) data path, a post-persist physical-to-logical drop recovery data path, or a unit test write data path.

17 . The system of claim 13 , wherein the operations further comprise:

interacting with a write message queue to retrieve TU data buffer addresses and TU address information in order to aggregate the plurality of TUs;

updating entries in a physical-to-logical (P2L) buffer associated with the TU address information; and

transmit the first backend command to the memory device.

18 . The system of claim 13 , wherein the operations further comprise at least one of:

enabling reuse of entries within a backend command buffer for subsequent host writes received from a host system; and

enabling reuse of a pool of pre-allocated backend commands in generating the first backend command.

19 . The system of claim 12 , wherein the streamer logic is to perform operations:

determining the second write messages comprise the second namespace identifier associated with the second block stripe;

accessing the second criteria set at a second location in memory;

aggregating the second plurality of TUs received in the second write messages, wherein the second criteria set enables accessing the plurality of TUs within a second format, of the second write messages, that depends on a data path associated with the second write messages; and

formatting the aggregated second plurality of TUs into the second backend command having a second format for transmittal to the memory device via the backend, wherein the second backend command is to direct the memory device in writing TU data, associated with the aggregated second plurality of TUs, to the second block stripe.

20 . A method comprising:

generating, by cursor logic of a memory sub-system controller, a criteria set associated with generating a backend command to be sent a memory device;

accessing the criteria set by a first streamer logic component, of multiple streamer logic components, which is coupled to the cursor logic and to a backend that communicates with the memory device;

aggregating, by the streamer logic, a plurality of translation units (TUs) received in one or more write messages, wherein the criteria set enables accessing the plurality of TUs within a first format, of the one or more write messages, that depends on a first data path associated with the one or more write messages, wherein the first data path is different than a second data path associated with a second streamer logic component of the multiple streamer logic components; and

formatting, by the streaming logic, the aggregated plurality of TUs into the backend command having a second format for transmittal to the memory device, wherein the backend command is to direct the memory device in writing TU data, associated with the plurality of TUs, to a memory array of the memory device.