IP Library Granted Patent US 12704969
Granted Patent B2
US 12704969 · App. 18/236,087 · Granted Aug 11, 2026

Asymmetric pass through voltage for reduction of cell-to-cell interference

Inventors: Augusto Benvenuti (Lallio, IT); Giovanni Maria Paolucci (Milan, IT); Alessio Urbani (Rome, IT); Gianpietro Carnevale (Bottanuco, IT); Aurelio Giancarlo Mauri (Meda, IT)
Assignee: Micron Technology, Inc.
G06F3/0619G06F3/0655G06F3/0679
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Quick Facts
Patent No.
US 12704969
App. No.
18/236,087
Granted
Aug 11, 2026
Kind
B2
Abstract

A memory access operation is initiated to read a set of target memory cells of a target wordline of the memory device. During the memory access operation, a read voltage level is caused to be applied to the target wordline. During the memory access operation, a first pass through voltage level is caused to be applied to a first wordline adjacent to the target wordline. During the memory access operation, a second pass through voltage is caused to be applied to a second wordline adjacent to the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level.

Claims (31)

1 . A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to perform operations comprising:

initiating a read operation to read a set of target memory cells of a target wordline of the memory device;

causing, during the read operation, a read voltage level to be applied to the target wordline;

causing, during application of the read voltage level to the target wordline, a first pass through voltage level to be applied to a first unselected wordline adjacent to the target wordline on a drain side of the target wordline; and

causing, during application of the read voltage level to the target wordline, a second pass through voltage level to be applied to a second unselected wordline adjacent to the target wordline on a source side of the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level, and wherein the first pass through voltage level is less than the second pass through voltage level during application of each of a plurality of different read voltage levels to the target wordline.

2 . The system of claim 1 , wherein the first pass through voltage level is the second pass through voltage level reduced by an offset value.

3 . The system of claim 1 , wherein the operations further comprise sensing a current level associated with the target wordline to confirm completion of the read operation.

4 . The system of claim 1 , wherein the first unselected wordline adjacent to the target wordline is programmed prior to the target wordline, and wherein the target wordline is programmed prior to the second unselected wordline adjacent to the target wordline.

5 . The system of claim 1 , wherein the read operation is a sub-operation of a program verify operation.

6 . The system of claim 1 , wherein the operations further comprise determining the read voltage level is greater than a lowest read voltage level.

7 . A method comprising:

initiating, by a processing device, a read operation to read a set of target memory cells of a target wordline of a memory device;

causing, during the read operation, a read voltage level to be applied to the target wordline;

causing, during application of the read voltage level to the target wordline, a first pass through voltage level to be applied to a first unselected wordline adjacent to the target wordline on a drain side of the target wordline; and

causing, during application of the read voltage level to the target wordline, a second pass through voltage level to be applied to a second unselected wordline adjacent to the target wordline on a source side of the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level, and wherein the first pass through voltage level is less than the second pass through voltage level during application of each of a plurality of different read voltage levels to the target wordline.

8 . The method of claim 7 , wherein the first pass through voltage level is the second pass through voltage level reduced by an offset value.

9 . The method of claim 7 , further comprising sensing a current level associated with the target wordline to confirm completion of the read operation.

10 . The method of claim 7 , wherein the first unselected wordline adjacent to the target wordline is programmed prior to the target wordline, and wherein the target wordline is programmed prior to the second unselected wordline adjacent to the target wordline.

11 . The method of claim 7 , wherein the read operation is a sub-operation of a program verify operation.

12 . The method of claim 7 , further comprising determining the read voltage level is greater than a lowest read voltage level.

13 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

initiating a read operation to read a set of target memory cells of a target wordline of a memory device;

causing, during the read operation, a read voltage level to be applied to the target wordline;

causing, during application of the read voltage level to the target wordline, a first pass through voltage level to be applied to a first unselected wordline adjacent to the target wordline on a drain side of the target wordline; and

causing, during application of the read voltage level to the target wordline, a second pass through voltage level to be applied to a second unselected wordline adjacent to the target wordline on a source side of the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level, and wherein the first pass through voltage level is less than the second pass through voltage level during application of each of a plurality of different read voltage levels to the target wordline.

14 . The non-transitory computer-readable storage medium of claim 13 , wherein the first pass through voltage level is the second pass through voltage level reduced by an offset value.

15 . The non-transitory computer-readable storage medium of claim 13 , wherein the operations further comprise sensing a current level associated with the target wordline to confirm completion of the read operation.

16 . The non-transitory computer-readable storage medium of claim 13 , wherein the first unselected wordline adjacent to the target wordline is programmed prior to the target wordline, and wherein the target wordline is programmed prior to the second unselected wordline adjacent to the target wordline.

17 . The non-transitory computer-readable storage medium of claim 13 , wherein the operations further comprise determining the read voltage level is greater than a lowest read voltage level.