Managing allocation of sub-blocks in a memory sub-system

1 . A system comprising:

a memory device comprising a plurality of dies; and

a processing device, operatively coupled with the memory device, to perform operations comprising:

performing a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks;

identifying, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device, wherein the first predefined value is determined to avoid using sub-blocks with similar error characteristics across the plurality of dies; and

performing the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.

2 . The system of claim 1 , further comprising:

receiving a request to perform a third programming operation;

identifying, based on a second predefined value, a third sub-block of a third die of the memory device, wherein the second predefined value is a shift in an index value of the second sub-block of the second die of the memory device; and

performing the third programming operation on a third set of cells associated with the third sub-block of the third die, wherein the third sub-block of the third die is associated with a different index value than the first sub-block of the first die and the second sub-block of the second die.

3 . The system of claim 1 , further comprising:

receiving a request to perform the first programming operation; and

receiving a request to perform the second programming operation.

4 . The system of claim 1 , wherein identifying, based on the first predefined value, the second sub-block of the second die of the memory device comprises:

retrieving the first predefined value from a look-up table associated with the memory device;

identifying a sub-block of the second die of the memory device, wherein the sub-block has an index value equivalent to the index value of the first sub-block of the first die;

applying the first predefined value to the index value of the identified sub-block of the second die of the memory device; and

in response to applying the first predefined value to the index value of the identified sub-block of the second die, identifying the second sub-block of the second die.

5 . The system of claim 1 , wherein identifying, based on the first predefined value, the second sub-block of the second die of the memory device comprises:

retrieving the first predefined value from a logical-to-physical (L2P) table associated with the memory device;

identifying a sub-block of the second die of the memory device, wherein the sub-block has an index value equivalent to the index value of the first sub-block of the first die;

applying the first predefined value to the index value of the identified sub-block of the second die of the memory device; and

in response to applying the first predefined value to the index value of the identified sub-block of the second die, identifying the second sub-block of the second die.

6 . The system of claim 1 , wherein the first predefined value is computed based on an error count associated with each die of the memory device.

7 . The system of claim 1 , wherein the first predefined value is computed using a hardware accelerator associated with the memory device.

8 . The system of claim 1 , further comprising:

identifying a sub-block on the second die that corresponds to a same physical location as the first sub-block on the first die; and

shifting from the identified sub-block based on the first predefined value to select the second sub-block.

9 . The system of claim 1 , wherein each die is a physically separate semiconductor substrate, wherein the sub-blocks are positioned at corresponding physical locations across the plurality of dies, wherein the shift is determined based on error characteristics shared by corresponding physical locations across the plurality of dies due to semiconductor manufacturing uniformity, and wherein shifting from sub-blocks with similar physical locations across the plurality of dies avoids clusters of high error rates due to manufacturing consistency across the plurality of dies.

10 . A method comprising:

computing a predefined value associated with each die of a memory device comprising a plurality of dies, wherein the predefined value is a shift in an index value of each sub-block associated with each die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks, wherein the predefined value is determined to avoid using sub-blocks with similar error characteristics across the plurality of dies;

receiving a request to perform a first programming operation;

identifying, based on the predefined value, a first sub-block of a first die of the memory device;

performing the first programming operation on a first set of cells associated with the first sub-block of the first die of the memory device;

identifying, based on the predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation; and

performing the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.

11 . The method of claim 10 , further comprising:

receiving a request to perform a third programming operation;

identifying, based on the predefined value, a third sub-block of a third die of the memory device; and

performing the third programming operation on a third set of cells associated with the third sub-block of the third die, wherein the third sub-block of the third die is associated with a different index value than the first sub-block of the first die and the second sub-block of the second die.

12 . The method of claim 10 , further comprising:

receiving a request to perform the first programming operation; and

receiving a request to perform the second programming operation.

13 . The method of claim 10 , wherein identifying, based on the predefined value, the second sub-block of the second die of the memory device comprises:

retrieving the predefined value from a look-up table associated with the memory device;

identifying a sub-block of the second die of the memory device, wherein the sub-block has an index value equivalent to the index value of the first sub-block of the first die;

applying the predefined value to the index value of the identified sub-block of the second die of the memory device; and

in response to applying the predefined value to the index value of the identified sub-block of the second die, identifying the second sub-block of the second die.

14 . The method of claim 10 , wherein identifying, based on the predefined value, the second sub-block of the second die of the memory device comprises:

retrieving the predefined value from a logical-to-physical (L2P) table associated with the memory device;

identifying a sub-block of the second die of the memory device, wherein the sub-block has an index value equivalent to the index value of the first sub-block of the first die;

applying the predefined value to the index value of the identified sub-block of the second die of the memory device; and

in response to applying the predefined value to the index value of the identified sub-block of the second die, identifying the second sub-block of the second die.

15 . The method of claim 10 , wherein the predefined value is computed based on an error count associated with each die of the memory device.

16 . The method of claim 10 , wherein the predefined value is computed using a hardware accelerator associated with the memory device.

17 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

performing a first programming operation on a first set of cells associated with a first sub-block of a first die of a memory device comprising a plurality of dies, wherein each die of the memory device comprises a plurality of sub-blocks;

identifying, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device, wherein the first predefined value is determined to avoid using sub-blocks with similar error characteristics across the plurality of dies; and

performing the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.

18 . The non-transitory computer-readable storage medium of claim 17 , wherein the processing device is to perform operations further comprising:

identifying, based on a second predefined value, a third sub-block of a third die of the memory device, wherein the second predefined value is a shift in an index value of the second sub-block of the second die of the memory device; and

performing a third programming operation on a third set of cells associated with the third sub-block of the third die, wherein the third sub-block of the third die is associated with a different index value than the first sub-block of the first die and the second sub-block of the second die.

19 . The non-transitory computer-readable storage medium of claim 17 , wherein the processing device is to perform operations further comprising:

receiving a request to perform the first programming operation; and

receiving a request to perform the second programming operation.

20 . The non-transitory computer-readable storage medium of claim 17 , wherein to identify, based on the first predefined value, the second sub-block of the second die of the memory device, the processing device is to perform operations further comprising:

retrieving the first predefined value from a look-up table associated with the memory device;

identifying a sub-block of the second die of the memory device, wherein the sub-block has an index value equivalent to the index value of the first sub-block of the first die;

applying the first predefined value to the index value of the identified sub-block of the second die of the memory device; and

in response to applying the first predefined value to the index value of the identified sub-block of the second die, identifying the second sub-block of the second die.

21 . The non-transitory computer-readable storage medium of claim 17 , wherein to identify, based on the first predefined value, the second sub-block of the second die of the memory device, the processing device is to perform operations further comprising:

retrieving the first predefined value from a logical-to-physical (L2P) table associated with the memory device;

identifying a sub-block of the second die of the memory device, wherein the sub-block has an index value equivalent to the index value of the first sub-block of the first die;

applying the first predefined value to the index value of the identified sub-block of the second die of the memory device; and

in response to applying the first predefined value to the index value of the identified sub-block of the second die, identifying the second sub-block of the second die.

22 . The non-transitory computer-readable storage medium of claim 17 , wherein the first predefined value is computed using a hardware accelerator associated with the memory device.