Apparatus with signal quality feedback
Methods, apparatuses, and systems related to operations for measuring the quality of a signal received by a memory device and providing feedback. The memory device can sample signal data using a predetermined sequence of timing offsets relative to a reference signal. Additionally or alternatively, the memory device can sample the signal data using a predetermined sequence of reference voltages. The memory device can provide feedback results to a controller regarding the quality of the sampled signal data.
1 . An apparatus, comprising:
a logic circuit configured to:
generate first sampling results based on sampling a first predetermined data pattern from a controller using a first setting; and
generate second sampling results based on sampling a second predetermined data pattern from the controller using a second setting; and
a communication circuit coupled to the logic circuit and configured to send the first sampling results and the second sampling results to the controller for adjusting a setting associated with subsequently communicated signals.
2 . The apparatus of claim 1 , wherein
the first setting includes (1) a first reference voltage level and/or (2) a first timing offset value relative to a period of a clock signal,
the second setting includes (1) a second reference voltage level and/or (2) a second timing offset value relative to the period of the clock signal, and
the apparatus is further configured to:
adjust the first reference voltage level to the second reference voltage level;
generate third sampling results based on sampling a third predetermined data pattern from the controller using the second reference voltage level and the first timing offset value relative to the clock signal; and
send the third sampling results to the controller.
3 . The apparatus of claim 1 , wherein the apparatus is further configured to:
generate a serialized output representative of a plot that includes the first sampling results and the second sampling results arranged according to reference voltage levels and timing offset values; and
send the serialized output to the controller.
4 . The apparatus of claim 1 , wherein the apparatus is further configured to:
determine one or more reference voltage levels and one or more timing offset values at which the first predetermined data pattern or the second predetermined data pattern has a sample output that matches a predetermined result.
5 . The apparatus of claim 1 , wherein the apparatus is further configured to:
determine one or more reference voltage levels and one or more timing offset values at which the first predetermined data pattern or the second predetermined data pattern does not have a sample output that matches a predetermined result.
6 . The apparatus of claim 1 , wherein the apparatus is further configured to:
determine a signal margin based on the first sampling results and the second sampling results.
7 . The apparatus of claim 1 , wherein the apparatus is a dynamic random-access memory (DRAM) that is coupled to the controller.
8 . A memory system, comprising:
a memory controller;
a memory array operably coupled to the memory controller and configured to:
generate first sampling results based on sampling a first predetermined signal pattern from the memory controller using a first setting;
generate second sampling results based on sampling a second predetermined signal pattern from the memory controller using a second setting; and
send the first sampling results and the second sampling results to the memory controller;
wherein
the memory controller and/or the memory array are/is configured to adjust a setting for communicating or processing subsequent signals according to the first sampling results and the second sampling results.
9 . The memory system of claim 8 , wherein
the first setting includes (1) a first reference voltage level and/or (2) a first timing offset value relative to a period of a clock signal,
the second setting includes (1) a second reference voltage level and/or (2) a second timing offset value relative to the period of the clock signal, and
the memory array is further configured to:
adjust the first reference voltage level to the second reference voltage level;
generate third sampling results based on sampling a third predetermined signal pattern using the second reference voltage level and the first timing offset value relative to the clock signal; and
send the third sampling results to the memory controller.
10 . The memory system of claim 8 , wherein the memory array is further configured to:
generate a serialized output representative of a plot that includes the first sampling results and the second sampling results arranged according to reference voltage levels and timing offset values; and
send the serialized output to the memory controller.
11 . The memory system of claim 8 , wherein the memory array is further configured to:
determine one or more reference voltage levels and one or more timing offset values at which the first predetermined signal pattern or the second predetermined signal pattern has a sample output that matches a predetermined result.
12 . The memory system of claim 8 , wherein the memory array is further configured to:
determine one or more reference voltage levels and one or more timing offset values at which the first predetermined signal pattern or the second predetermined signal pattern does not have a sample output that matches a predetermined result.
13 . The memory system of claim 8 , wherein the memory array is further configured to:
determine a signal margin based on the first sampling results and the second sampling results.
14 . The memory system of claim 8 , wherein the memory array is a dynamic random-access memory (DRAM).
15 . A method of operating an apparatus, the method comprising:
generating first sampling results based on sampling a first predetermined data pattern using a first setting;
generating second sampling results based on sampling a second predetermined data pattern using a second setting; and
sending the first sampling results and the second sampling results to a controller for adjusting a setting associated with subsequently communicated signals.
16 . The method of claim 15 ,
wherein the first setting includes (1) a first reference voltage level and/or (2) a first timing offset value relative to a period of a clock signal,
wherein the second setting includes (1) a second reference voltage level and/or (2) a second timing offset value relative to the period of the clock signal,
the method further comprising:
adjusting the first reference voltage level to the second reference voltage level;
generating third sampling results based on sampling a third predetermined data pattern using the second reference voltage level and the first timing offset value relative to the clock signal; and
sending the third sampling results to the controller.
17 . The method of claim 15 , further comprising:
generating a serialized output representative of a plot that includes the first sampling results and the second sampling results arranged according to reference voltage levels and timing offset values; and
sending the serialized output to the controller.
18 . The method of claim 15 , further comprising:
determining one or more reference voltage levels and one or more timing offset values at which the first predetermined data pattern or the second predetermined data pattern has a sample output that matches a predetermined result.
19 . The method of claim 15 , further comprising:
determining one or more reference voltage levels and one or more timing offset values at which the first predetermined data pattern or the second predetermined data pattern does not have a sample output that matches a predetermined result.
20 . The method of claim 15 , further comprising:
determining a signal margin based on the first sampling results and the second sampling results.