IP Library › Granted Patent US 12,704,981

Granted Patent B2

US 12,704,981 · App. 18/761,287 · Granted Aug 11, 2026

Methods of voltage regulation, electronic apparatuses and storage media

Inventors: Yusheng Zou (Wuhan, CN); Congjian Pei (Wuhan, CN); Xiaodong Xu (Wuhan, CN)

Assignee: Yangtze Memory Technologies Co., Ltd.

G06F3/0625 G06F3/0634 G06F3/0673 G11C5/147

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Quick Facts

Patent No.: US 12,704,981
App. No.: 18/761,287
Granted: Aug 11, 2026
Kind: B2

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Abstract

The present disclosure provides methods, electronic apparatuses and storage media for voltage regulation. An example method includes acquiring a current working state of the memory system, and reducing a voltage provided to the memory system in response to the current working state being a light-load working state.

Claims (54)

1 . A method of voltage regulation, wherein the method of voltage regulation is applied to an electronic apparatus comprising a memory system, and comprises:

acquiring, through a processor directly coupled to the memory system, a current working state of the memory system, wherein the current working state comprises a light-load working state and a heavy-load working state; and

reducing, by adjusting a first power supply voltage provided to a memory controller of the memory system and a second power supply voltage provided to a memory of the memory system, a voltage directly provided to the memory system in response to the current working state being the light-load working state.

2 . The method of claim 1 , wherein the electronic apparatus further comprises a power management IC, and the reducing the voltage provided to the memory system comprises:

sending a first voltage adjustment instruction to the power management IC; and

reducing the voltage provided to the memory system from a standard working voltage to a lower limit working voltage by the power management IC in response to the first voltage adjustment instruction.

3 . The method of claim 2 , wherein

the reducing the voltage provided to the memory system from the standard working voltage to the lower limit working voltage comprises:

reducing the first power supply voltage provided to the memory controller from a standard working voltage of the first power supply voltage to a lower limit working voltage of the first power supply voltage, and reducing the second power supply voltage provided to the memory from a standard working voltage of the second power supply voltage to a lower limit working voltage of the second power supply voltage, by the power management IC.

4 . The method of claim 3 , wherein the reducing the voltage provided to the memory system from the standard working voltage to the lower limit working voltage further comprises:

reducing the second power supply voltage provided to the memory from the standard working voltage of the second power supply voltage to zero, and reducing the first power supply voltage provided to the memory controller from the standard working voltage of the first power supply voltage to the lower limit working voltage of the first power supply voltage, by the power management IC.

5 . The method of claim 1 , wherein before the acquiring the current working state of the memory system, the method further comprises:

acquiring the current working state of the memory system in response to not sending an operating instruction to the memory system within a preset time threshold, wherein the operating instruction is to instruct the memory system to enter the heavy-load working state.

6 . The method of claim 1 , wherein the acquiring the current working state of the memory system comprises:

sending a state information acquisition instruction to the memory system, and acquiring state information fed back by the memory system; and

determining the current working state of the memory system according to the state information.

7 . The method of claim 6 , wherein after the reducing the voltage provided to the memory system, the method further comprises:

sending a second voltage adjustment instruction to a power management IC in response to at least one operating instruction sent to the memory system or the state information fed back by the memory system being the heavy-load working state; and

adjusting the voltage provided to the memory system from a lower limit working voltage to a standard working voltage by the power management IC in response to the second voltage adjustment instruction.

8 . The method of claim 1 , wherein the light-load working state comprises a plurality of sub-working states including a standby state, a hibernate state, an idle state, a sleep state and a deep sleep state, wherein lower limit working voltages corresponding to different ones of the sub-working states are different.

9 . An electronic apparatus, comprising:

a memory system; and

at least one processor coupled with the memory system, wherein the at least one processor is configured to:

acquire, through a processor directly coupled to the memory system, a current working state of the memory system, wherein the current working state comprises a light-load working state and a heavy-load working state; and

reduce, by adjusting a first power supply voltage provided to a memory controller of the memory system and a second power supply voltage provided to a memory of the memory system, a voltage directly provided to the memory system in response to the current working state being the light-load working state.

10 . The electronic apparatus of claim 9 , wherein the electronic apparatus further comprises a power management IC coupled with the at least one processor, and the at least one processor is configured to:

send a first voltage adjustment instruction to the power management IC; and

the power management IC is configured to:

reduce the voltage provided to the memory system from a standard working voltage to a lower limit working voltage in response to the first voltage adjustment instruction.

11 . The electronic apparatus of claim 10 , wherein the power management IC is configured to:

reduce the first power supply voltage provided to the memory controller from a standard working voltage of the first power supply voltage to a lower limit working voltage of the first power supply voltage, and reduce the second power supply voltage provided to the memory system from a standard working voltage of the second power supply voltage to a lower limit working voltage of the second power supply voltage.

12 . The electronic apparatus of claim 11 , wherein the power management IC is further configured to:

reduce the second power supply voltage provided to the memory from the standard working voltage of the second power supply voltage to zero, and reduce the first power supply voltage provided to the memory controller from the standard working voltage of the first power supply voltage to the lower limit working voltage of the first power supply voltage.

13 . The electronic apparatus of claim 9 , wherein the at least one processor is further configured to:

acquire the current working state of the memory system in response to not sending an operating instruction to the memory system within a preset time threshold, wherein the operating instruction is to instruct the memory system to enter the heavy-load working state.

14 . The electronic apparatus of claim 9 , wherein the at least one processor is configured to:

send a state information acquisition instruction to the memory system, and acquire state information fed back by the memory system; and

determine the current working state of the memory system according to the state information.

15 . The electronic apparatus of claim 14 , wherein the at least one processor is further configured to:

send a second voltage adjustment instruction to a power management IC in response to at least one operating instruction sent to the memory system or the state information fed back by the memory system being the heavy-load working state; and

the power management IC is further configured to:

adjust the voltage provided to the memory system from a lower limit working voltage to a standard working voltage in response to the second voltage adjustment instruction.

16 . The electronic apparatus of claim 9 , wherein the light-load working state comprises a plurality of sub-working states including a standby state, a hibernate state, an idle state, a sleep state and a deep sleep state, wherein lower limit working voltages corresponding to different ones of the sub-working states are different.

17 . A non-transitory, computer readable storage medium, comprising a program stored therein, wherein the program is executable to control an electronic apparatus comprising a memory system where the non-transitory computer readable storage medium is located to perform operations comprising:

18 . The non-transitory, computer readable storage medium of claim 17 , wherein before the acquiring the current working state of the memory system, the operations further comprises:

19 . The non-transitory, computer readable storage medium of claim 17 , wherein the acquiring the current working state of the memory system comprises:

sending a state information acquisition instruction to the memory system, and acquiring state information fed back by the memory system; and

determining the current working state of the memory system according to the state information.

20 . The non-transitory, computer readable storage medium of claim 19 , wherein after the reducing the voltage provided to the memory system, the operations further comprise: