Memory device, method of calibrating signal level thereof, and memory system having the same

1 . A memory device comprising:

a transceiver configured to receive or transmit data in a manner selected from a first signaling or a second signaling through a data channel; and

a ratio of level separation mismatch (RLM) controller configured to;

maintain at least two gaps between signal levels of the second signaling to be identical to each other when transferring data from the transceiver to an external device,

perform pull-up code and pull-down code calibrations using a ZQ calibration for the first signaling,

perform an additional most significant bit (MSB) code calibration using an MSB additional driver connected to a first node for the second signaling, and

perform an additional least significant bit (LSB) code calibration using an LSB additional driver connected to the first node for the second signaling.

2 . The memory device of claim 1 , wherein the RLM controller is configured to receive an RLM calibration request from the external device.

3 . The memory device of claim 1 , wherein the RLM controller is configured to perform RLM calibration using the ZQ calibration and the MSB and LSB additional drivers in response to an RLM calibration request from the external device.

4 . The memory device of claim 1 , wherein the first signaling is a 2-level signal and the second signaling is at least a 3-level signal.

5 . The memory device of claim 1 , wherein the RLM controller includes:

a resistor connected between the first node and a ground terminal;

a first comparator configured to output a first comparison voltage by comparing a first adjusted voltage of the first node to a first reference voltage;

a second comparator configured to output a second comparison voltage by comparing a second adjusted voltage of a second node to a second reference voltage;

a first code generator configured to generate a pull-up code, a most significant bit (MSB) additional code, or a least significant bit (LSB) additional code, corresponding to the first comparison voltage;

a second code generator configured to generate a pull-down code corresponding to the second comparison voltage;

a first MSB pull-up driver connected between a power supply terminal and the first node and configured to control driving capability for at least a first higher bit according to the pull-up code;

a first LSB pull-up driver connected between the power supply terminal and the first node and configured to control driving capability for at least a first lower bit according to the pull-up code;

a first MSB pull-down driver connected between the first node and the ground terminal and configured to control driving capability for at least a first higher bit according to the pull-down code;

a first LSB pull-down driver connected between the first node and the ground terminal and configured to control driving capability for at least a first lower bit according to the pull-down code;

a second MSB pull-up driver connected between the power supply terminal and the second node and configured to control driving capability for at least a second higher bit according to the pull-up code;

a second LSB pull-up driver connected between the power supply terminal and the second node and configured to control driving capability for at least a second lower bit according to the pull-up code;

a second MSB pull-down driver connected between the second node and the ground terminal and configured to control driving capability for at least a second higher bit according to the pull-down code;

a second LSB pull-down driver connected between the second node and the ground terminal and configure to control driving capability for at least a second lower bit according to the pull-down code;

the MSB additional driver configured to control driving capability for at least a first higher bit according to the MSB additional code; and

the LSB additional driver configured to control driving capability for at least a first lower bit according to the LSB additional code.

6 . The memory device of claim 5 , further comprising:

a first selector configured to select one of a plurality of signal levels as the first reference voltage.

7 . The memory device of claim 5 , wherein the second signaling is a multilevel signaling, and

wherein the multilevel signaling is a pulse amplitude modulation level-4 (PAM4) signaling.

8 . The memory device of claim 7 , further comprising:

a first selector configured to select one of a first signal level, a second signal level, and a third signal level as the first reference voltage; and

a second selector configured to select the first signal level as the second reference voltage.

9 . The memory device of claim 8 , wherein the first signal level is higher than the second signal level,

wherein the second signal level is higher than the third signal level,

wherein the third signal level is higher than a level of the ground terminal, and

wherein the level of the ground terminal is a fourth signal level.

10 . A memory system comprising:

at least one memory device; and

a controller configured to control the at least one memory device,

wherein the at least one memory device includes:

a first transceiver configured to receive or transmit data in a manner selected from a first signaling or a second signaling through a data channel; and

a first ratio of level separation mismatch (RLM) controller configured to:

maintain at least two gaps between signal levels of the second signaling to be identical to each other when transferring data from the first transceiver to the controller,

perform pull-up code and pull-down code calibrations using a ZQ calibration for the first signaling,

perform an additional most significant bit (MSB) code calibration using an MSB additional driver connected to a first node for the second signaling, and

perform an additional least significant bit (LSB) code calibration using an LSB additional driver connected to the first node for the second signaling.

11 . The memory system of claim 10 , wherein the controller includes a second RLM controller and a second transceiver configured to transmit or receive the data through the data channel.

12 . The memory system of claim 11 , wherein the second RLM controller is configured to maintain at least two gaps between signal levels of the second signaling to be identical to each other when transmitting data from the second transceiver to the memory device.

13 . The memory system of claim 10 , wherein the controller is configured to transmit an RLM calibration request to the memory device in response to a request from a host.

14 . An operating method of a memory device, the method comprising:

transmitting data to a controller using one of a first signaling and a second signaling through a data channel;

maintaining at least two gaps between signal levels of the second signaling to be identical to each other during the transmitting data;

performing an additional most significant bit (MSB) code calibration, using an MSB additional driver connected to a first node for the second signaling; and

performing an additional least significant bit (LSB) code calibration using an LSB additional driver connected to the first node for the second signaling.

15 . The operating method of claim 14 , further comprising:

selecting one of the first signaling and the second signaling.

16 . The operating method of claim 14 , further comprising:

performing pull-up code and pull-down code calibrations, using a ZQ calibration for the first signaling.

17 . The operating method of claim 14 , wherein the first signaling is a 2-level signal and the second signaling is at least a 3-level signal.