Read refresh techniques for nonvolatile memory devices

1 . A method of operating a memory device, comprising the steps of:

preparing a plane that includes a plurality of memory blocks with arrays of memory cells;

programming the memory cells of a plurality of the memory blocks to create a plurality of programmed memory blocks while leaving at least one spare memory block in the plane that is not programmed;

performing a plurality of read operations on the programmed memory blocks;

without having reprogrammed the memory cells of any of the plurality of programmed memory blocks, detecting a trigger event;

in response to detecting the trigger event, relocating data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block so that the at least one spare memory block becomes a programmed memory block and then erasing the selected memory block so that the selected memory block becomes a new spare memory block; and

repeating the step of relocating data from the selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erasing the selected memory block so that the selected memory block becomes the new spare memory block for all of the programmed memory blocks in the plane until all of the data in the plane has been relocated.

2 . The method as set forth in claim 1 , wherein the step of detecting the trigger event includes maintaining a timer of an interval since the step of programming the memory cells of the plurality of memory blocks to create the plurality of programmed memory blocks; and

establishing that the timer exceeds a predetermined threshold.

3 . The method as set forth in claim 2 , wherein after the step of relocating data from the selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erasing the selected memory block so that the selected memory block becomes the new spare memory block is repeated for all of the programmed memory blocks, the method continues with the step of resetting the timer.

4 . The method as set forth in claim 1 , wherein the step of detecting the trigger event includes detecting that a read counter associated with the selected memory block exceeds a predetermined threshold.

5 . The method as set forth in claim 1 , wherein relocating data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erasing the selected memory block so that the selected memory block becomes a new spare memory block includes the steps of:

reading data programmed into the memory cells of a selected word line of the selected memory block; and

programming the data into the memory cells of the at least one spare memory block.

6 . A memory device, comprising:

a plane that includes a plurality of memory blocks with arrays of memory cells, the plurality of memory blocks including a plurality of programmed memory blocks containing data and at least one spare memory block in the plane that does not contain data;

control circuitry that is configured to:

perform a plurality of read operations on the programmed memory blocks;

without having reprogrammed the memory cells of any of the plurality of programmed memory blocks, detect a trigger event;

in response to detecting the trigger event, relocate data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block so that the at least one spare memory block becomes a programmed memory block and then erase the selected memory block so that the selected memory block becomes a new spare memory block; and

repeating the process of relocating data from the selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erasing the selected memory block so that the selected memory block becomes the new spare memory block for all of the programmed memory blocks in the plane until all of the data in the plane has been relocated.

7 . The memory device as set forth in claim 6 , wherein the control circuitry maintains a timer of an interval since the memory cells of the plurality of memory blocks are programmed to create the plurality of programmed memory blocks; and

wherein the control circuitry detects the trigger event in response to the timer exceeding a predetermined threshold.

8 . The memory device as set forth in claim 6 , wherein after relocating data from the selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erasing the selected memory block so that the selected memory block becomes the new spare memory block, the control circuitry is configured to repeat this step for all of the programmed memory blocks, the control circuitry is then configured to reset the timer.

9 . The memory device as set forth in claim 6 , wherein to detect the trigger event, the control circuitry is configured to detect that a read counter associated with the selected memory block exceeds a predetermined threshold.

10 . The memory device as set forth in claim 6 , wherein relocating data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erasing the selected memory block so that the selected memory block becomes a new spare memory block includes the steps of:

reading data programmed into the memory cells of a selected word line of the selected memory block; and

programming the data into the memory cells of the at least one spare memory block.

11 . A computing system, comprising:

a processing unit;

a plurality of flash packages, each of the flash packages including a plurality of planes that have memory blocks with arrays of memory cells, the plurality of memory blocks including a plurality of programmed memory blocks containing data and at least one spare memory block that does not contain data;

control circuitry that is configured to:

perform a plurality of read operations on the programmed memory blocks;

without having reprogrammed the memory cells of any of the plurality of programmed memory blocks, detect a trigger event;

in response to detecting the trigger event, relocate data from a selected memory block of the plurality of programmed memory blocks to the at least one spare memory block in the same plane so that the at least one spare memory block becomes a programmed memory block and then erase the selected memory block so that the selected memory block becomes a new spare memory block; and

repeat the process of relocating data from the selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erasing the selected memory block so that the selected memory block becomes the new spare memory block for all of the programmed memory blocks in the plane until all of the data in the plane has been relocated.

12 . The computing system as set forth in claim 11 , wherein the control circuitry maintains a timer of an interval since the memory cells of the plurality of memory blocks are programmed to create the plurality of programmed memory blocks; and

wherein the control circuitry detects the trigger event in response to the timer exceeding a predetermined threshold.

13 . The computing system as set forth in claim 11 , wherein after relocating data from the selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erasing the selected memory block so that the selected memory block becomes the new spare memory block is repeated for all of the programmed memory blocks in the same plane, the control circuitry is configured to reset the timer.

14 . The computing system as set forth in claim 11 , wherein to detect the trigger event, the control circuitry is configured to detect that a read counter associated with the selected memory block exceeds a predetermined threshold.

15 . The computing system as set forth in claim 14 , wherein the control circuitry only relocates data from the selected memory block of the plurality of programmed memory blocks to the at least one spare memory block and then erases the selected memory block only on the selected memory block; and wherein the control circuitry is further configured to:

establish the at least one spare memory block as a new selected memory block;

reset the read counter associated with the new selected memory block; and

perform read operations on the plurality of programmed memory blocks.