Multiple rank DRAMs on a same module side

1 . An apparatus, comprising:

a dual-rank dual-inline memory module (DIMM) device, comprising a first plurality of dual-rank memory chip sets each comprising a first-ranked memory chip and a second-ranked memory chip and a second plurality of dual-rank memory chip sets each comprising a first-ranked memory chip and a second-ranked memory chip;

wherein:

the first plurality of dual-rank memory chip sets are positioned on a top side of the dual-rank DIMM device;

the second plurality of dual-rank memory chip sets are positioned on a bottom side of the dual-rank DIMM device;

the first-ranked memory chips of the first plurality of dual-rank memory chip sets and the second-ranked memory chips of the second plurality of dual-rank memory chip sets are positioned toward a first horizontal direction of the dual-rank DIMM device; and

the first-ranked memory chips of the second plurality of dual-rank memory chip sets and the second-ranked memory chips of the first plurality of dual-rank memory chip sets are positioned toward a second horizontal direction of the dual-rank DIMM device different than the first horizontal direction.

2 . The apparatus of claim 1 , wherein the first-ranked memory chips of the first plurality of dual-rank memory chip sets on the top side and the first-ranked memory chips of the second plurality of dual-rank memory chip sets on the bottom side are accessed concurrently.

3 . The apparatus of claim 1 , wherein the second-ranked memory chips of the first plurality of dual-rank memory chip sets on the top side and the second-ranked memory chips of the second plurality of dual-rank memory chip sets on the bottom side are accessed concurrently.

4 . An apparatus, comprising:

a dual-rank dual-inline memory module (DIMM) device, comprising:

a top layer comprising:

a first plurality of first-ranked memory chips of a first plurality of memory chip sets; and

a first plurality of second-ranked memory chips of the respective first plurality of memory chip sets, wherein each of the first plurality of memory chip sets comprise a pair of one of the first plurality of first-ranked memory chips and one of the first plurality of second-ranked memory chips; and

a bottom layer comprising:

a second plurality of first-ranked memory chips of a second plurality of memory chip sets; and

a second plurality of second-ranked memory chips of the respective second plurality of memory chip sets, wherein each of the second plurality of memory chip sets comprise a pair of one of the second plurality of first-ranked memory chips and one of the second plurality of second-ranked memory chips, wherein:

each pair of memory chips of each of the first-ranked and the second-ranked memory chips are connected using a micro-strip; and

each of the pairs in the first plurality of memory chip sets in the top side is connected to a top goldfinger through a strip line layer nearest a top layer of a printed circuit board (PCB) of the dual-rank DIMM device.

5 . The apparatus of claim 4 , wherein the plurality of memory chip sets are a plurality of volatile memory devices.

6 . The apparatus of claim 5 , wherein the plurality of volatile memory devices are dynamic random access memory (DRAM) devices.

7 . The apparatus of claim 4 , wherein each of the pairs in the first plurality of memory chip sets is connected to the top goldfinger through:

a first microvia that connects each of the pairs to the strip line layer; and

a second microvia that connects the strip line layer to the top goldfinger.

8 . The apparatus of claim 4 , wherein each of the pairs in the second plurality of memory chip sets in the top side is connected to a bottom goldfinger through a strip line layer nearest a bottom layer of a printed circuit board (PCB) of the dual-rank DIMM device.

9 . The apparatus of claim 4 , wherein:

the first plurality of first-ranked memory chips and the second plurality of first-ranked memory chips are accessed concurrently;

the first plurality of second-ranked memory chips and the second plurality of second-ranked memory chips are accessed concurrently; and

the first and second plurality of first-ranked memory chips are not accessed concurrently to the first and second plurality of second-ranked memory chips being accessed.

10 . A method, comprising:

accessing a first plurality of first-ranked memory chips of a first plurality of memory chip sets concurrently with a second plurality of first-ranked memory chips of a second plurality of memory chip sets, wherein:

the first plurality of memory chip sets are on a top side of a dual-rank dual-inline memory module (DIMM) device; and

the second plurality of memory chip sets are on a bottom side of the dual-rank DIMM device; and

accessing a first plurality of second-ranked memory chips of the first plurality of memory chip sets concurrently with a second plurality of second-ranked memory chips of the second plurality of memory chip sets, wherein

the first plurality of first-ranked memory chips of the first plurality of memory chip sets and the second plurality of second-ranked memory chips of the second plurality of memory chip sets are positioned toward a first horizontal direction of the dual-rank DIMM device; and

the second plurality of first-ranked memory chips of the second plurality of memory chip sets and the first plurality of second-ranked memory chips of the first plurality of memory chip sets are positioned toward a second horizontal direction of the dual-rank DIMM device different than the first horizontal direction.

11 . The method of claim 10 , wherein:

the first plurality of first-ranked memory chips of the first plurality of memory chip sets and the second plurality of first-ranked memory chips of the second plurality of memory chip sets are positioned toward a first horizontal direction of the dual-rank DIMM device; and

the first plurality of second-ranked memory chips of the first plurality of memory chip sets and the second plurality of second-ranked memory chips of the second plurality of memory chip sets are positioned toward a second horizontal direction of the dual-rank DIMM device different than the first horizontal direction.