Quick charge loss mitigation using two-pass controlled delay

1 . A method comprising:

writing, by a memory controller, a first subset of data bits of a first set of data bits at a first bit density to a first memory block of a memory device during a first pass of programming;

determining, by the memory controller, that a delay threshold is satisfied; and

in response to determining that the delay threshold is satisfied, writing, by the memory controller, a second subset of data bits of the first set of data bits at a second bit density to the first memory block during a second pass of programming of the memory device, wherein the second bit density is greater than the first bit density.

2 . The method of claim 1 , wherein determining that the delay threshold is satisfied comprises determining a difference between a first time of writing the first subset of data bits to a first wordline and a current time satisfies a threshold time difference.

3 . The method of claim 1 , wherein determining that the delay threshold is satisfied comprises determining a time difference is satisfied by measuring a difference between a first time stamp and a second time stamp, wherein measuring the difference comprises:

generating a first time stamp representing a write to a first wordline;

generating a second time stamp representing a write to a last wordline;

determining a time difference between the first time stamp and the second time stamp; and

comparing the time difference with the delay threshold.

4 . The method of claim 1 , further comprising:

determining that a time difference between a time of writing the first subset of data bits in a first pass of programming and a current time does not satisfy the delay threshold; and

writing the second subset of data bits of the first set of data bits to a buffer for at least the delay threshold less the time difference, wherein writing the second subset of data bits of the first set of data bits to a buffer is prior to determining that a delay threshold is satisfied.

5 . The method of claim 1 , wherein determining that the delay threshold is satisfied comprises determining that a threshold number of computing operations have been completed after writing a first subset of data bits of the first set to a first memory block of the memory during a first pass of programming.

6 . The method of claim 1 , wherein the delay threshold is based on an electrical charge loss of the memory.

7 . The method of claim 6 , further comprising increasing a programming voltage for each bit of the second subset of data bits based on the electrical charge loss of the memory.

8 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

write a first subset of data bits of a first set of data bits at a first bit density to a first memory block of a memory device during a first pass of programming;

determine that a delay threshold is satisfied; and

in response to determining that the delay threshold is satisfied, write a second subset of data bits of the first set of data bits at a second bit density to the first memory block during a second pass of programming of the memory device, wherein the second bit density is greater than the first bit density.

9 . The non-transitory computer-readable storage medium of claim 8 , wherein to determine that the delay threshold is satisfied, the instructions further cause the processing device to determine a difference between a first time of writing the first subset of data bits to a first wordline and a second time of a current time satisfies a threshold time difference.

10 . The non-transitory computer-readable storage medium of claim 8 , wherein to determine that the delay threshold is satisfied, the instructions further cause the processing device to determine that a number of computing operations have been completed after writing a first subset of data bits of the first set to a first memory block of the memory during a first pass of programming satisfies a threshold number of computing operations.

11 . The non-transitory computer-readable storage medium of claim 8 , wherein to determine that the delay threshold is satisfied, the instructions further cause the processing device to:

determine a time difference is satisfied by measuring a difference between a first time stamp and a second time stamp, wherein measuring the difference further causes the processing device to:

generate a first time stamp representing a write to a first wordline;

generate a second time stamp representing a current time;

determine a time difference between the first time stamp and the second time stamp; and

compare the time difference with the delay threshold.

12 . The non-transitory computer-readable storage medium of claim 8 , the instructions further causing the processing device to:

determine that a time difference between a time stamp and a current time does not satisfy the delay threshold; and

write the second subset of data bits of the first set of data bits to a buffer for at least the delay threshold less the time difference, wherein writing the second subset of data bits of the first set of data bits to a buffer is prior to determining that a delay threshold is satisfied.

13 . The non-transitory computer-readable storage medium of claim 8 , wherein the delay threshold is based on an electrical charge loss of the memory.

14 . The non-transitory computer-readable storage medium of claim 8 , the instructions further causing the processing device to increase a programming voltage for each bit of the second subset of data bits based on an electrical charge loss of the memory.

15 . A system comprising:

a memory device; and

a processing device, operatively coupled with a plurality of memory device to:

write a first subset of data bits of a first set of data bits at a first bit density to a first memory block of a memory device during a first pass of programming;

generate a first time stamp representing a start time of a write of the first subset of data bits;

generate a second time stamp representing a current system time;

determine that a delay threshold is satisfied using a time difference between the first time stamp and the second time stamp; and

in response to determining that the delay threshold is satisfied, write a second subset of data bits of the first set of data bits at a second bit density to the first memory block during a second pass of programming of the memory device, wherein the second bit density is greater than the first bit density.

16 . The system of claim 15 , the processing device further to:

determine that a time difference between the first time stamp and a third time stamp does not satisfy the delay threshold; and

write the second subset of data bits of the first set of data bits to a buffer for at least the delay threshold less the time difference, wherein writing the second subset of data bits of the first set of data bits to a buffer is prior to determining that the delay threshold is satisfied.

17 . The system of claim 16 , the processing device further to:

receive a second set of data bits after writing the first subset of data bits and before writing the second subset of data bits;

determining, after receiving the second set of data bits, that the time difference between the first time stamp and a current system time does not satisfy the delay threshold; and

writing a third subset of data bits from the second set of data bits, wherein writing the third subset of data bits is prior to determining that a delay threshold is satisfied.

18 . The system of claim 15 , wherein the delay threshold is based on an electrical charge loss of the memory.

19 . The system of claim 15 , the processing device further to increase a programming voltage for each bit of the second subset of data bits based on an electrical charge loss of the memory.

20 . The system of claim 15 , the processing device further to determine that the delay threshold is satisfied comprises determining that a number of computing operations have been completed after writing a first subset of data bits of the first set to a first memory block of the memory during a first pass of programming satisfies the delay threshold.