Completion queue handling by host controller for storage device
A host system is coupled to a storage device and manages completion queues (CQs) for the storage device. The host system includes a host controller and memory that stores submission queues (SQs) and the CQs. The host controller fetches a command from a given SQ that corresponds to a target CQ. The host controller saves the command in an SQ internal buffer of the host controller, calculates an available capacity (AC) associated with the given SQ for the host system to store a response to the command from the storage device, and sends the command to the storage device when the available capacity is non-zero. The available capacity is calculated based on, at least in part, available slots in the target CQ.
1 . A method performed by a host controller in a host system to manage completion queues (CQs) for a storage device coupled to the host system, comprising:
fetching a command from a given submission queue (SQ) that corresponds to a target CQ, wherein the given SQ and the target CQ are in a memory of the host system;
saving the command in an SQ internal buffer of the host controller;
calculating, by the host controller in the host system before sending the command to the storage device for execution, an available capacity (AC) associated with the given SQ in the host system to store a response to the command from the storage device, wherein the available capacity is calculated based on, at least in part, available slots in the target CQ, and wherein the available capacity is calculated based on, at least in part, available slots in a CQ internal buffer of the host controller for buffering responses from the storage device; and
sending the command to the storage device for execution when the available capacity associated with the given SQ is non-zero.
2 . The method of claim 1 , wherein the available capacity is calculated based on, at least in part, a difference between a given threshold for the given SQ and the number of slots in the target CQ that are occupied by responses to commands originating from the given SQ.
3 . The method of claim 2 , wherein the available capacity is the minimum of the available slots in the target CQ and the difference.
4 . The method of claim 1 , wherein the available capacity is the minimum of (1) the available slots in the CQ internal buffer plus the available slots in the target CQ, and (2) a difference between a given threshold (TH) for the given SQ and the number of slots in the target CQ and the CQ internal buffer that are occupied by commands originating from the given SQ.
5 . The method of claim 1 , wherein the CQ internal buffer is commonly shared by all of the CQs in the host system.
6 . The method of claim 1 , wherein the host system includes a plurality of CQ internal buffers for respective ones of the CQs.
7 . The method of claim 1 , wherein sending the command further comprises:
sending the command when the number of active commands in an active command queue of the storage device is within a predetermined maximum value.
8 . The method of claim 1 , further comprising:
stopping the command from the given SQ from being sent to the storage device when there is zero available capacity in the host system to store the response.
9 . The method of claim 1 , wherein the host controller communicates with the storage device according to a Universal Flash Storage (UFS) standard.
10 . A system operative to manage completion queues (CQs) for a storage device, comprising:
the storage device; and
a host system coupled to the storage device, the host system further comprising:
one or more processors;
a host controller circuit coupled to the one or more processors; and
host memory to store submission queues (SQs) and the CQs, wherein the host controller circuit is operative to:
fetch a command from a given SQ that corresponds to a target CQ in the host memory;
save the command in an SQ internal buffer of the host controller circuit;
calculate, before sending the command to the storage device for execution, an available capacity (AC) associated with the given SQ in the host system to store a response to the command from the storage device, wherein the available capacity is calculated based on, at least in part, available slots in the target CQ, and wherein the available capacity is calculated based on, at least in part, available slots in a CQ internal buffer of the host controller for buffering responses from the storage device; and
send the command to the storage device for execution when the available capacity associated with the given SQ is non-zero.
11 . The system of claim 10 , wherein the available capacity is calculated based on, at least in part, a difference between a given threshold for the given SQ and the number of slots in the target CQ that are occupied by responses to commands originating from the given SQ.
12 . The system of claim 11 , wherein the available capacity is the minimum of the available slots in the target CQ and the difference.
13 . The system of claim 10 , wherein the available capacity is the minimum of (1) the available slots in the CQ internal buffer plus the available slots in the target CQ, and (2) a difference between a given threshold (TH) for the given SQ and the number of slots in the target CQ and the CQ internal buffer that are occupied by commands originating from the given SQ.
14 . The system of claim 10 , wherein the CQ internal buffer is commonly shared by all of the CQs in the host system.
15 . The system of claim 10 , wherein the host system includes a plurality of CQ internal buffers for respective ones of the CQs.
16 . The system of claim 10 , wherein the host controller circuit is further operative to:
send the command when the number of active commands in an active command queue of the storage device is within a predetermined maximum value.
17 . The system of claim 10 , wherein the host controller circuit is further operative to:
stop the command from the given SQ from being sent to the storage device when there is zero available capacity in the host system to store the response.
18 . The system of claim 10 , wherein the host controller circuit communicates with the storage device according to a Universal Flash Storage (UFS) standard.