Method for automatically generating a sequence of Nmax instructions in assembly language, the sequence being executable error-free by a multi-core processor
A method for automatically generating a sequence of Nmax instructions in assembly language, the sequence being executable error-free by a multi-core processor, the method comprising steps of: initializing registers of the processor, then selecting a first instruction of the predetermined sequence, optionally at random; and selecting an N+1 th instruction among an instruction to read from a memory connected to the cores of the processor by a memory bus, an instruction to write to said memory, and a local instruction using only the registers of the processors, according to rules and to priorities between the rules, the rules using respective differences between statistical-metric values of statistical metrics of a memory access pattern of the sequence of N previous instructions having statistical-metric values, and setpoint values.
1 . A method for iteratively generating automatically a sequence of Nmax instructions in assembly language, the sequence of Nmax instructions being executable error-free by a multi-core processor, the method comprising steps of:
initializing registers of a multi-core processor, then selecting a first instruction of a predetermined sequence or at random;
selecting after the first instruction, provided that N<Nmax, an N+1th instruction among instructions to read from a memory connected to cores of the multi-core processor by a memory bus, an instruction to write to said memory, and a local instruction using only the registers of the multi-core processor and the selecting being according to rules and to priorities between said rules; and
integrating the N+1 th instruction in the sequence of Nmax instructions in assembly language into an execution loop to generate executable software or a stub,
wherein said rules using respective differences between statistical-metric values of statistical metrics of a memory access pattern (P) of a sequence of N previous instructions having statistical-metric values, and setpoint values; and
wherein the rules comprising a first test rule, if a memory intensity (Im) is greater than a memory-intensity setpoint (Im_c), then the N+1 th instruction selected is a local instruction, and otherwise, the N+1 th instruction selected is a read access instruction (R) or a write access instruction (W).
2 . The method according to claim 1 , wherein the statistical metrics of the memory access pattern of the sequence of N previous instructions comprise:
a memory intensity (Im) corresponding to a ratio of a number of read access instructions (R) or write access instructions (W) to a total number of instructions N;
a read/memory ratio (Rwr) corresponding to the ratio of the read access instructions (R) to memory access instructions (R, W); and
an access Shannon entropy (E) of the memory access pattern (P), representative of a random aspect of memory addresses accessed.
3 . The method according to claim 2 , wherein the statistical metrics of the memory access pattern of the sequence of N previous instructions further comprise an interleaving (Iv) of the read access instructions (R) and of the write access instructions (W).
4 . The method according to claim 1 , wherein the rules comprise rules applied after the first test rule, in any order:
a second test rule, if a read/memory ratio (Rwr) is greater than a read/memory-ratio setpoint (Rwr_c), then the N+1 th instruction selected is a read access instruction (R), and otherwise, the N+1 th instruction selected is a write access instruction (W);
a third test rule, if a Shannon entropy (Ep) of the memory access pattern (P) is greater than a Shannon-entropy setpoint (Ep_c), then a memory address of the N+1 th instruction is selected so as to reduce an entropy E, through an address already in use or an address that is already known, and otherwise, the memory address of the N+1 th instruction is selected at random; and
a fourth test rule, if an interleaving (Iv) is greater than an interleaving setpoint (Iv_c), then the N+1 th instruction selected is a read access instruction (R) or a write access instruction (W) of a same access type as the N th instruction, and otherwise, the N+1 th instruction selected is a read access instruction (R) or a write access instruction (W) opposite to an access type of the N th instruction.
5 . The method according to claim 1 wherein selection of the N+1 th instruction is performed based on current contents of processor registers and memory content updated after execution of the N th instruction.
6 . The method according to claim 1 wherein the rules are configured to prevent execution exceptions arising from invalid register usage or invalid memory addressing.
7 . The method according to claim 1 further comprising integrating a generated instruction sequence into an execution loop executed on the multi-core processor to evaluate memory bus contention behavior.
8 . The method according to claim 1 wherein the statistical metrics correspond to contention behavior on a shared memory bus arbitrated among processor cores.