Speculative execution using a page-level tracked load order queue

1 . A method for speculative execution using multiple queues including at least a first queue and a second queue, the method comprising:

adding a first entry to the first queue for a first load instruction based on the first load instruction targeting a memory area outside of a current program stack, wherein each entry in the first queue identifies a particular memory address; and

adding a second entry to the second queue for a second load instruction based on the second load instruction targeting the current program stack, wherein each entry in the second queue identifies a page of memory.

2 . The method of claim 1 , further comprising:

updating an activity counter of the second entry in response to a third load instruction that targets the current program stack and targets a page address identified in the second entry.

3 . The method of claim 1 , further comprising removing, based on a state of a re-order buffer, the second entry from the second queue.

4 . The method of claim 3 , wherein removing, based on the state of the re-order buffer, the second entry from the second queue comprises:

decrementing, based on the state of the re-order buffer, an activity counter of the second entry; and

removing the second entry from the second queue based on the activity counter.

5 . The method of claim 1 , further comprising determining that the second load instruction targets a memory address relative to a stack pointer.

6 . The method of claim 1 , wherein the second load instruction is associated with a first thread, and the method further comprises:

receiving a query from a second thread indicating a store instruction target; and

initiating a pipeline flush in response to the store instruction target comprising a page address identified in the second entry.

7 . The method of claim 1 , wherein the second queue is a page-level tracked load order queue.

8 . A load store unit for speculative execution using multiple queues including at least a first queue and a second queue, the load store unit configured to:

add a first entry to the first queue for a first load instruction based on the first load instruction targeting a memory area outside of a current program stack, wherein each entry in the first queue identifies a particular memory address; and

add a second entry to the second queue in response to a second load instruction that targets the current program stack, wherein each entry in the second queue identifies a page of memory.

9 . The load store unit of claim 8 , wherein the load store unit is further configured to:

update an activity counter of the second entry in response to a third load instruction that targets the current program stack and target a page address identified in the second entry.

10 . The load store unit of claim 8 , wherein the load store unit is further configured to remove, based on a state of a re-order buffer, the second entry from the second queue.

11 . The load store unit of claim 10 , wherein the load store unit removes the second entry from the second queue by:

decrementing, based on the state of the re-order buffer, an activity counter of the second entry; and

removing the second entry from the second queue based on the activity counter.

12 . The load store unit of claim 8 , wherein the load store unit is further configured to determine that the second load instruction targets a memory address relative to a stack pointer.

13 . The load store unit of claim 8 , wherein the second load instruction is associated with a first thread, and the load store unit is further configured to:

receive a query from a second thread indicating a store instruction target; and

initiate a pipeline flush in response to the store instruction target comprising a page address identified in the second entry.

14 . A processor for speculative execution using multiple queues, comprising:

a first queue comprising a plurality of entries each identifying a particular memory address, wherein the processor is configured to add a first entry to the first queue for a first load instruction based on the first load instruction targeting a memory area outside of a current program stack; and

a second queue comprising a plurality of entries each identifying a page of memory, wherein the processor is configured to add a second entry to the second queue for a second load instruction based on the second load instruction targeting the current program stack.

15 . The processor of claim 14 , wherein the processor is further configured to:

update an activity counter of the second entry in response to a third load instruction that targets the current program stack and targets a page address identified in the second entry.

16 . The processor of claim 14 , wherein the processor is further configured to remove, based on a state of a re-order buffer, the second entry from the second queue.

17 . The processor of claim 16 , wherein the processor removes the second entry from the second queue by:

decrementing, based on the state of the re-order buffer, an activity counter of the second entry; and

removing the second entry from the second queue based on the activity counter.

18 . The processor of claim 14 , wherein the second load instruction targets a memory address relative to a stack pointer.

19 . The processor of claim 14 , wherein the second load instruction is associated with a first thread, and the processor is further configured to:

receive a query from a second thread indicating a store instruction target; and

initiate a pipeline flush in response to the store instruction target comprising a page address identified in the second entry.

20 . The processor of claim 14 , wherein the second queue is a page-level tracked load order queue.