IP Library › Granted Patent US 12705058
Granted Patent B2
US 12705058 · App. 19/032,886 · Granted Aug 11, 2026

Apparatuses, systems, and methods for mode register page access modes

Inventors: Randall J. Rooney (Boise, ID); David R. Brown (Allen, TX)
Assignee: Micron Technology, Inc.
G06F9/30189G06F9/355
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Quick Facts
Patent No.
US 12705058
App. No.
19/032,886
Granted
Aug 11, 2026
Kind
B2
Abstract

Embodiments disclosed herein provide techniques for entering, remaining, and exiting a mode register page access (MRPA) mode in a semiconductor device (e.g., a memory device). A command is used to cause the memory device to enter the MRPA mode when accessing the mode register, and a subsequent command is used to cause the memory device to remain in the MRPA mode for continued access to the mode register. While in the MRPA mode, subsequent commands enable the memory device to be accessed using a mode register address for a read command, or a mode register address and an operation code (OP code) for a write command.

Claims (50)

1 . An apparatus, comprising:

external terminals configured to receive a plurality of commands associated with an operation, the operation comprising a mode register read operation or a mode register write operation; and

one or more mode registers each configured to perform the operation, wherein:

a first command in the plurality of commands causes the apparatus to enter a mode register page access mode to enable the one or more registers to be accessed as a page, the first command providing a mode register page address and a mode register address in the mode register page to access; and

a second command in the plurality of commands causes the apparatus to remain in the mode register page access mode and provides a subsequent mode register address in the mode register page to access.

2 . The apparatus of claim 1 , wherein a third command in the plurality of commands causes the apparatus to exit the mode register page access mode.

3 . The apparatus of claim 2 , wherein the third command comprises an external control signal set at a particular state to cause the apparatus to exit the mode register page access mode.

4 . The apparatus of claim 1 , wherein the first command and the second command are mode register page access commands that cause the apparatus to perform a mode register page access operation.

5 . The apparatus of claim 1 , wherein a fourth command in the plurality of commands is a direct mode register access command that causes the apparatus to perform a direct mode register access operation.

6 . The apparatus of claim 1 , wherein the first command comprises an external control signal set at a particular state to cause the apparatus to enter the mode register page access mode.

7 . The apparatus of claim 1 , wherein the second command comprises an external control signal set at a particular state to cause the apparatus to remain in the mode register page access mode.

8 . The apparatus of claim 1 , wherein the first command comprises one or more command address bits each set at a particular state to cause the apparatus to enter the mode register page access mode.

9 . The apparatus of claim 8 , wherein the one or more command address bits comprise multiple command address bits that define a mode register address.

10 . The apparatus of claim 1 , wherein the second command comprises one or more command address bits each set at a particular state to cause the apparatus to exit the mode register page access mode.

11 . The apparatus of claim 10 , wherein the one or more command address bits comprise multiple command address bits that define a mode register address.

12 . The apparatus of claim 1 , wherein the one or more mode registers comprise two or more mode registers that are associated with a similar function.

13 . A method, comprising:

receiving a first command to perform a first operation of a first type, the first type comprising a mode register read operation or a mode register write operation;

based on the first command, causing a mode register to enter a mode register page access mode;

receiving a second command to perform a second operation of the first type; and

based on the second command, causing the mode register to remain in the mode register page access mode,

wherein:

the first command provides a mode register page address and a first mode register address in the mode register page to access; and

the second command provides a second mode register address in the mode register page to access.

14 . The method of claim 13 , further comprising receiving a third command to cause the mode register to exit the mode register page access mode.

15 . The method of claim 14 , wherein the third command comprises an external control signal set at a particular state to cause the mode register to exit the mode register page access mode.

16 . The method of claim 13 , wherein:

the first command comprises an external control signal set at a particular state to cause the mode register to enter the mode register page access mode; or

the second command comprises an external control signal set at a particular state to cause the mode register to remain in the mode register page access mode.

17 . The method of claim 13 , wherein:

the first command comprises one or more command address bits each set at a particular state to cause the mode register to enter the mode register page access mode; or

the second command comprises one or more command address bits each set at a particular state to cause the mode register to exit the mode register page access mode.

18 . The method of claim 13 , wherein:

the first command comprises a plurality of mode register address bits each set at a particular state to cause the mode register to enter the mode register page access mode; or

the second command comprises a plurality of mode register address bits each set at a particular state to cause the mode register to exit the mode register page access mode.

19 . A controller configured to transmit commands to a memory device, the commands comprising:

a first command to cause the memory device to enter a mode register page access mode; and

a second command to cause the memory device to remain in the mode register page access mode,

wherein:

the first command comprises a first set of bits:

at least one bit in the first set of bits causes the memory device to enter the mode register page access mode;

a first portion of the first set of bits provides a mode register page address;

a second portion of the first set of bits provides a mode register address in the mode register page to access;

the second command comprises a second set of bits:

at least one bit in the second set of bits causes the memory device to remain in the mode register page access mode; and

a third portion of the second set of bits provides a mode register address in the mode register page to access.

20 . The apparatus of claim 19 , wherein the at least one bit in the first set of bits is an external control signal.

21 . The apparatus of claim 19 , wherein the at least one bit in the second set of bits is an external control signal.

22 . The apparatus of claim 19 , wherein the at least one bit in the first set of bits comprises one or more command address bits.

23 . The apparatus of claim 19 , wherein the at least one bit in the second set of bits comprises one or more command address bits.