IP Library › Granted Patent US 12705061
Granted Patent B2
US 12705061 · App. 19/016,197 · Granted Aug 11, 2026

Application programming interface to indicate accelerator error handlers

Inventors: Karthik Raghavan Ravi (Bangalore, IN); Ashutosh Jain (Bengaluru, IN); Rahul Suresh (Bangalore, IN)
Assignee: NVIDIA Corporation
G06F9/3861G06F9/3836G06F9/3877G06F9/541
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Quick Facts
Patent No.
US 12705061
App. No.
19/016,197
Granted
Aug 11, 2026
Kind
B2
Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.

Claims (41)

1 . One or more processors, comprising: circuitry to:

receive an Application Programming Interface (“API”) call, an input parameter of the API indicating error handler program code;

in response to the API call, register the error handler program code to handle one or more asynchronous errors from one or more accelerators, wherein the one or more accelerators and one or more Graphics Processing Units (GPUs) are within a heterogeneous processor; and

cause the error handler program code to be performed in response to one or more asynchronous errors from the one or more accelerators within the heterogeneous processor.

2 . The one or more processors of claim 1 , wherein the input parameter comprises a pointer to a function to be registered as the error handler program code.

3 . The one or more processors of claim 1 , wherein the circuitry is further to register one or more memory buffers as error notification buffers to be polled for error information generated by the one or more accelerators.

4 . The one or more processors of claim 1 , wherein the circuitry is further to:

receive a second Application Programming Interface (“API”) call having a second input parameter indicating one or more memory regions usable to store error information generated by the one or more accelerators; and

in response to the second API call, identify, in the one or more memory regions, error information generated by the one or more accelerators.

5 . The one or more processors of claim 1 , wherein the circuitry is further to:

receive a second Application Programming Interface (“API”) call having a second input parameter indicating one or more memory regions usable to store error information generated by the one or more accelerators; and

in response to the second API call, poll for one or more errors from the one or more accelerators in the one or more memory regions by checking for error information generated by the one or more accelerators in the one or more memory regions.

6 . The one or more processors of claim 1 , wherein the one or more accelerators comprise at least one of: a deep learning accelerator (DLA), a programmable vision accelerator (PVA), or a field-programmable gate array (FPGA).

7 . The one or more processors of claim 1 , wherein the one or more accelerators are packaged on a system-on-chip (SoC) together with at least one of: the one or more processors or the one or more GPUs.

8 . The one or more processors of claim 1 , wherein the one or more processors include a central processing unit (CPU).

9 . The one or more processors of claim 1 , wherein the error handler program code comprises one or more instructions that, if performed, cause the one or more accelerators within the heterogeneous processor to perform one or more computational operations in response to the one or more asynchronous errors.

10 . The one or more processors of claim 1 , wherein the one or more asynchronous errors are to be generated by the one or more accelerators within the heterogeneous processor and one or more other errors are to be generated by one or more other accelerators, and the one or more other errors are to be handled by one or more other error handlers.

11 . A system, comprising:

one or more processors to:

receive an Application Programming Interface (“API”) call, an input parameter of the API indicating error handler program code;

in response to the API call, register the error handler program code to handle one or more asynchronous errors from one or more accelerators, wherein the one or more accelerators and one or more Graphics Processing Units (GPUs) are within a heterogeneous processor; and

cause the error handler program code to be performed in response to one or more asynchronous errors from the one or more accelerators within the heterogeneous processor.

12 . The system of claim 11 , wherein the input parameter comprises a pointer to a function to be registered as the error handler program code.

13 . The system of claim 11 , wherein the one or more processors are further to register one or more memory buffers as error notification buffers to be polled for error information generated by the one or more accelerators.

14 . The system of claim 11 , wherein the one or more processors are further to:

receive a second Application Programming Interface (“API”) call having a second input parameter indicating one or more memory regions usable to store error information generated by the one or more accelerators; and

in response to the second API call, identify, in the one or more memory regions, error information generated by the one or more accelerators.

15 . The system of claim 11 , wherein the one or more processors are further to:

receive a second Application Programming Interface (“API”) call having a second input parameter indicating one or more memory regions usable to store error information generated by the one or more accelerators; and

in response to the second API call, poll for one or more errors from the one or more accelerators in the one or more memory regions by checking for error information generated by the one or more accelerators in the one or more memory regions.

16 . A method, comprising:

receiving an Application Programming Interface (“API”) call, an input parameter of the API indicating error handler program code;

in response to the API call, registering the error handler program code to handle one or more asynchronous errors from one or more accelerators, wherein the one or more accelerators and one or more Graphics Processing Units (GPUs) are within a heterogeneous processor; and

causing the error handler program code to be performed in response to one or more asynchronous errors from the one or more accelerators within the heterogeneous processor.

17 . The method of claim 16 , wherein the input parameter comprises a pointer to a function to be registered as the error handler program code.

18 . The method of claim 16 , further comprising:

registering one or more memory buffers as error notification buffers to be polled for error information generated by the one or more accelerators.

19 . The method of claim 16 , further comprising:

receiving a second Application Programming Interface (“API”) call having a second input parameter indicating one or more memory regions usable to store error information generated by the one or more accelerators; and

in response to the second API call, identifying, in the one or more memory regions, error information generated by the one or more accelerators.

20 . The method of claim 16 , wherein the one or more accelerators comprise at least one of: a deep learning accelerator (DLA), a programmable vision accelerator (PVA), or a field-programmable gate array (FPGA).