Hardware-accelerated atomic data structures
A processor includes an accelerated access circuit, a data structure, and a hardware scheduler. The data structure is managed by software and bound to the accelerated access circuit. The hardware scheduler is configured to schedule, on the accelerated access circuit, a work item requesting access to the data structure. The accelerated access circuit is configured to receive a request from the work item to access the data structure. Responsive to the request, the accelerated access circuit is further configured to serialize access by the work item to the data structure thereby preventing other work items from accessing the data structure.
1 . A processor, comprising:
an accelerated access circuit;
a data structure managed by software; and
a hardware scheduling circuit configured to schedule, on the accelerated access circuit, a work item requesting access to the data structure,
wherein the accelerated access circuit is configured to:
receive a request from the work item to access the data structure; and
responsive to the request, enforce exclusive access to the data structure at the accelerated access circuit by blocking any other work item from being scheduled to access the data structure until the requested access completes.
2 . The processor of claim 1 , wherein the data structure is bound to the accelerated access circuit.
3 . The processor of claim 1 , wherein the accelerated access circuit is configured to enforce exclusive access by serializing access to the data structure, including:
configuring the hardware scheduling circuit to refrain from scheduling, on the accelerated access circuit, additional work items requesting access to the data structure.
4 . The processor of claim 3 , wherein the accelerated access circuit is further configured to:
responsive to the requested access having completed, configure the hardware scheduling circuit to schedule, on the accelerated access circuit, another work item requesting access to the data structure.
5 . The processor of claim 1 , wherein the accelerated access circuit is configured to enforce exclusive access by serializing access to the data structure, including:
setting a locking mechanism associated with the data structure.
6 . The processor of claim 5 , wherein the locking mechanism is internal to the accelerated access circuit.
7 . The processor of claim 5 , wherein the accelerated access circuit is further configured to:
responsive to the access having completed, resetting the locking mechanism associated with the data structure.
8 . The processor of claim 1 , wherein the accelerated access circuit is configured to enforce exclusive access by serializing access to the data structure, including:
performing one or more operations on the data structure indicated by the request.
9 . The processor of claim 8 , wherein the accelerated access circuit is further configured to:
return results of the one or more operations to the work item.
10 . The processor of claim 1 , wherein the data structure is only accessible by the accelerated access circuit.
11 . The processor of claim 1 , wherein the accelerated access circuit is bound to a plurality of data structures managed by software.
12 . A method, comprising:
receiving, by an accelerated access circuit in a processing system, a request from a work item generated by a processor of the processing system to access a data structure managed by software; and
responsive to the request, enforcing, by the accelerated access circuit, exclusive access to the data structure at the accelerated access circuit by blocking any other work item from being scheduled to access the data structure until the requested access completes.
13 . The method of claim 12 , wherein enforcing exclusive access comprises serializing access to the data structure by:
configuring, by the accelerated access circuit, a hardware scheduling circuit of the processing system to refrain from scheduling, on the accelerated access circuit, additional work items requesting access to the data structure.
14 . The method of claim 13 , wherein responsive to the requested access having completed, configuring, by the accelerated access circuit, the hardware scheduling circuit to schedule, on the accelerated access circuit, another work item requesting access to the data structure.
15 . The method of claim 12 , wherein enforcing exclusive access comprises serializing access to the data structure by:
setting, by the accelerated access circuit, a locking mechanism associated with the data structure.
16 . The method of claim 15 , wherein responsive to the access having completed, resetting, by the accelerated access circuit, the locking mechanism associated with the data structure.
17 . The method of claim 12 , wherein enforcing exclusive access comprises serializing access to the data structure by:
performing, by the accelerated access circuit, one or more operations on the data structure indicated by the request.
18 . The method of claim 12 , further comprising:
binding the data structure only to the accelerated access circuit.
19 . The method of claim 12 , further comprising:
binding the accelerated access circuit to a plurality of data structures managed by software.
20 . A processor, comprising:
at least one compute unit comprising an accelerated access circuit;
a data structure managed by software and maintained within the accelerated access circuit, wherein the data structure is only accessible through the accelerated access circuit; and
a hardware scheduling circuit configured to schedule, on the accelerated access circuit, a work item requesting access to the data structure,
wherein the accelerated access circuit is configured to:
receive a request from the work item to access the data structure; and
responsive to the request, enforce exclusive access to the data structure at the accelerated access circuit by blocking any other work item from being scheduled to access the data structure until the requested access completes.