IP Library Granted Patent US 12705130
Granted Patent B2
US 12705130 · App. 18/618,639 · Granted Aug 11, 2026

Partially good block handling in a memory device

Inventors: Yu-Chung Lien (San Jose, CA); Jiangli Zhu (San Jose, CA); Zhenming Zhou (San Jose, CA)
Assignee: Micron Technology, Inc.
G06F11/0775G06F11/0727
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Quick Facts
Patent No.
US 12705130
App. No.
18/618,639
Granted
Aug 11, 2026
Kind
B2
Abstract

A programming failure is detected at a block of a memory device. Based on detecting the programming failure, the block is determined to be partially good based on a number of failed bytes in the block. An unfailing portion of the block is identified in response to determining the block is partially good. A record indicating the block is partially good and identifying the unfailing portion of the block is stored.

Claims (67)

1 . A memory sub-system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, configured to perform operations comprising:

detecting a programming failure at a block of the memory device, the block comprising a central row decoder that divides the block into a first half and a second half;

based on detecting the programming failure, determining the block is partially good based on a number of failed bytes in the block;

identifying an unfailing half of the block in response to determining the block is partially good;

storing a record indicating the block is partially good and identifying the unfailing half of the block;

receiving a command to perform a data operation on the block;

accessing the record in response to the command;

based on the command indicating the block is partially good, disabling a failed half of the block, the disabling of the failed half of the block comprising disabling one or more switch transistors of the central row decoder that correspond to the failed half of the block; and

executing the data operation on the unfailing half of the block while the failed half of the block is disabled.

2 . The memory sub-system of claim 1 , wherein:

the disabling of the failed half comprises disabling the first half of the block by disabling the one or more switch transistors, the one or more switch transistors corresponding to the first half of the block.

3 . The memory sub-system of claim 1 , wherein the operations further comprise identifying the failed half of the block based on the record.

4 . The memory sub-system of claim 1 , wherein identifying the unfailing half of the block comprises:

performing a first scan of the first half of the block; and

performing a second scan of the second half of the block.

5 . The memory sub-system of claim 1 , wherein determining the block is a partially good block comprises determining the number of failed bytes satisfies a threshold condition.

6 . The memory sub-system of claim 5 , wherein:

the threshold condition defines a threshold number of failed bytes; and

determining the number of failed bytes satisfies the threshold condition comprises determining the number of failed bytes does not exceed the threshold number of failed bytes.

7 . The memory sub-system of claim 1 , wherein identifying the unfailing half of the block comprises:

determining a first number of failed bytes in a first half of the block;

determining a second number of failed bytes in a second half of the block; and

comparing the first number of failed bytes to the second number of failed bytes.

8 . The memory sub-system of claim 7 , wherein comparing the first number of failed bytes to the second number of failed bytes comprises:

determining a difference between the first number of failed bytes to the second number of failed bytes; and

determining whether the difference satisfies a threshold condition.

9 . The memory sub-system of claim 1 , wherein the central row decoder horizontally divides the block into a left half and a right half.

10 . The memory sub-system of claim 1 , wherein the operations further comprise performing a count of failed bytes scan on the block to determine the number of failed bytes.

11 . A method comprising:

executing, by a processing device, a program command on a block of a memory device, the block of the memory device comprising a central row decoder that devices the block into a first half and a second half;

detecting, by the processing device, a programming failure at the block of the memory device based on executing the program command;

based on detecting the programming failure, determining, by the processing device, the block is partially good based on a number of failed bytes in the block;

identifying, by the processing device, the first half or the second half as an unfailing half of the block in response to determining the block is partially good;

storing, by the processing device, a record indicating the block is partially good and identifying the unfailing half of the block;

receiving a command to perform a data operation on the block;

accessing the record in response to the command;

based on the command indicating the block is partially good, disabling a failed half of the block, the disabling of the failed half of the block comprising disabling one or more switch transistors of the central row decoder that correspond to the failed half of the block; and

executing the data operation on the unfailing half of the block while the failed half of the block is disabled.

12 . The method of claim 11 , wherein:

the disabling of the failed half comprises disabling the first half of the block by disabling the one or more switch transistors, the one or more switch transistors corresponding to the first half of the block.

13 . The method of claim 11 , wherein the operations further comprise identifying the failed half of the block based on the record.

14 . The method of claim 11 , wherein identifying the unfailing half of the block comprises:

performing a first scan of the first half of the block; and

performing a second scan of the second half of the block.

15 . The method of claim 11 , wherein determining the block is a partially good block comprises determining the number of failed bytes satisfies a threshold condition.

16 . The method of claim 15 , wherein:

the threshold condition defines a threshold number of failed bytes; and

determining the number of failed bytes satisfies the threshold condition comprises determining the number of failed bytes does not exceed the threshold number of failed bytes.

17 . The method of claim 11 , wherein identifying the unfailing half of the block comprises:

determining a first number of failed bytes in a first half of the block;

determining a second number of failed bytes in a second half of the block; and

comparing the first number of failed bytes to the second number of failed bytes.

18 . The method of claim 16 , wherein comparing the first number of failed bytes to the second number of failed bytes comprises:

determining a difference between the first number of failed bytes to the second number of failed bytes; and

determining whether the difference satisfies a threshold condition.

19 . The method of claim 11 , wherein the the central row decoder horizontally divides the block into a left half and a right half.

20 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising:

detecting a programming failure at a block of a memory device, the block of the memory device comprising a central row decoder that horizontally divides the block into a first half and a second half;

based on detecting the programming failure, determining the block is partially good based on a number of failed bytes in the block;

determining the first half of the block is an unfailing half of the block in response to determining the block is partially good;

storing a record indicating the block is partially good and identifying the first half as the unfailing half of the block;

receiving a command to perform a data operation on the block;

accessing the record in response to the command;

based on the command indicating the block is partially good, disabling a failed half of the block, the disabling of the failed half of the block comprising disabling one or more switch transistors of a row decoder that correspond to the failed half of the block; and

executing the data operation on the unfailing half of the block while the failed half of the block is disabled.